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B-1
B
Using Performance Monitoring
Events
Performance monitoring events provides facilities to characterize the
interaction between programmed sequences of instructions and different
microarchitectural sub-systems. Performance monitoring events are
described in Chapter 18 and Appendix A of the IA-32 Intel®
Architecture Software Developer’s Manual, Volume 3B.
The first part of this chapter provides information on how to use
performance events specific to Pentium 4 and Intel Xeon processors
based on the Intel NetBurst microarchitecture. The second half
discusses similar topics using performance events available on Intel
Core Solo and Intel Core Duo processors.
Pentium 4 Processor Performance Metrics
The descriptions of the Intel Pentium 4 processor performance metrics
use terminology that are specific to the Intel NetBurst microarchitecture
and to the implementation in the Pentium 4 and Intel Xeon processors.
The following sections explain the terminology specific to Pentium 4
and Intel Xeon processors, usage notes that apply to counting clock
cycles, and notes for using some of the performance metrics dealing
with bus, memory and Hyper-Threading Technology. The performance
metrics for IA-32 processors with CPUID signature that matches family
encoding 15, mode encoding 0, 1, 2 or 3 are listed in Tables B-1 through
Table B-4. Several new performance metrics are available to IA-32
processors with CPUID signature that matches family encoding 15,
mode encoding 3; these performance metrics are listed in Table B-5.