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DDR3THIN-MN-XXX 21 Doc. Rev. 1.11
Group
Name
Signal
Name
DDR3
Pin #
TLA
Input
Group
Name
Signal
Name
DDR3
Pin #
TLA
Input
WrA_DatHi WR_A_DQ63 234 S_D2:0 WrA_DatLo WR_A_DQ31 156 M_D0:6
(Hex) WR_A_DQ62 233 S_D2:1 (Hex) WR_A_DQ30 155 M_D0:3
WR_A_DQ61 228 S_D2:5 WR_A_DQ29 150 S_C0:0
WR_A_DQ60 227 S_Q1 WR_A_DQ28 149 S_C0:1
WR_A_DQ59 115 S_D2:2 WR_A_DQ27 37 M_D0:4
WR_A_DQ58 114 S_D2:3 WR_A_DQ26 36 M_D0:1
WR_A_DQ57 109 S_D2:7 WR_A_DQ25 31 S_C0:2
WR_A_DQ56 108 S_D3:0 WR_A_DQ24 30 S_C0:3
WR_A_DQ55 225 S_D3:2 WR_A_DQ23 147 S_C0:4
WR_A_DQ54 224 S_D3:3 WR_A_DQ22 146 S_C0:5
WR_A_DQ53 219 S_D3:7 WR_A_DQ21 141 S_C1:2
WR_A_DQ52 218 S_D1:5 WR_A_DQ20 140 S_C1:3
WR_A_DQ51 106 S_D3:1 WR_A_DQ19 28 S_C0:6
WR_A_DQ50 105 S_D3:4 WR_A_DQ18 27 S_C0:7
WR_A_DQ49 100 S_D1:7 WR_A_DQ17 22 S_C1:1
WR_A_DQ48 99 S_D1:6 WR_A_DQ16 21 S_C1:4
WR_A_DQ47 216 S_D1:4 WR_A_DQ15 138 S_C1:6
WR_A_DQ46 215 S_D1:1 WR_A_DQ14 137 S_C1:7
WR_A_DQ45 210 S_D0:7 WR_A_DQ13 132 S_E1:4
WR_A_DQ44 209 S_D0:6 WR_A_DQ12 131 S_E1:1
WR_A_DQ43 97 S_D1:3 WR_A_DQ11 19 S_C1:5
WR_A_DQ42 96 S_D1:2 WR_A_DQ10 18 S_E1:7
WR_A_DQ41 91 S_D0:5 WR_A_DQ9 13 S_E1:3
WR_A_DQ40 90 S_D0:4 WR_A_DQ8 12 S_E1:2
WR_A_DQ39 207 S_D0:3 WR_A_DQ7 129 S_E1:0
WR_A_DQ38 206 S_D0:2 WR_A_DQ6 128 S_E0:7
WR_A_DQ37 201 M_C0:1 WR_A_DQ5 123 S_E0:3
WR_A_DQ36 200 M_C0:4 WR_A_DQ4 122 S_E0:2
WR_A_DQ35 88 S_D0:1 WR_A_DQ3 10 S_CK2
WR_A_DQ34 87 S_D0:0 WR_A_DQ2 9 S_E0:5
WR_A_DQ33 83 M_C0:6 WR_A_DQ1 4 S_E0:1
WR_A_DQ32 81 M_C0:7 WR_A_DQ0 3 S_E0:0
Table 1 – B_DDR3D_2D (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.)
Notes:
1. All signals on this page are required for accurate post-processing of acquired data
2. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair