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DDR3THIN-MN-XXX 34 Doc. Rev. 1.11
Group
Name
Signal
Name
DDR3
Pin#
TLA
Input
Group
Name
Signal
Name
DDR3
Pin#
TLA
Input
1_RdB_DatHi 1_RD_B_DQ63 234 S2_A0:0^1 1_RdB_DatLo 1_RD_B_DQ31 156 S2_D2:6^1
(Hex) 1_RD_B_DQ62 233 S2_A0:1^1 (Hex) 1_RD_B_DQ30 155 S2_D2:3^1
1_RD_B_DQ61 228 S2_A0:5^1 1_RD_B_DQ29 150 S2_E2:0^1
1_RD_B_DQ60 227 S2_CK1^1 1_RD_B_DQ28 149 S2_E2:1^1
1_RD_B_DQ59 115 S2_A0:2^1 1_RD_B_DQ27 37 S2_D2:4^1
1_RD_B_DQ58 114 S2_A0:3^1 1_RD_B_DQ26 36 S2_D2:1^1
1_RD_B_DQ57 109 S2_A0:7^1 1_RD_B_DQ25 31 S2_E2:2^1
1_RD_B_DQ56 108 S2_A1:0^1 1_RD_B_DQ24 30 S2_E2:3^1
1_RD_B_DQ55 225 S2_A1:2^1 1_RD_B_DQ23 147 S2_E2:4^1
1_RD_B_DQ54 224 S2_A1:3^1 1_RD_B_DQ22 146 S2_E2:5^1
1_RD_B_DQ53 219 S2_A1:7^1 1_RD_B_DQ21 141 S2_E3:2^1
1_RD_B_DQ52 218 S2_D1:5^1 1_RD_B_DQ20 140 S2_E3:3^1
1_RD_B_DQ51 106 S2_A1:1^1 1_RD_B_DQ19 28 S2_E2:6^1
1_RD_B_DQ50 105 S2_A1:4^1 1_RD_B_DQ18 27 S2_E2:7^1
1_RD_B_DQ49 100 S2_D1:7^1 1_RD_B_DQ17 22 S2_E3:1^1
1_RD_B_DQ48 99 S2_D1:6^1 1_RD_B_DQ16 21 S2_E3:4^1
1_RD_B_DQ47 216 S2_D1:4^1 1_RD_B_DQ15 138 S2_E3:6^1
1_RD_B_DQ46 215 S2_D1:1^1 1_RD_B_DQ14 137 S2_E3:7^1
1_RD_B_DQ45 210 S2_D0:7^1 1_RD_B_DQ13 132 S2_E1:4^1
1_RD_B_DQ44 209 S2_D0:6^1 1_RD_B_DQ12 131 S2_E1:1^1
1_RD_B_DQ43 97 S2_D1:3^1 1_RD_B_DQ11 19 S2_E3:5^1
1_RD_B_DQ42 96 S2_D1:2^1 1_RD_B_DQ10 18 S2_E1:7^1
1_RD_B_DQ41 91 S2_D0:5^1 1_RD_B_DQ9 13 S2_E1:3^1
1_RD_B_DQ40 90 S2_D0:4^1 1_RD_B_DQ8 12 S2_E1:2^1
1_RD_B_DQ39 207 S2_D0:3^1 1_RD_B_DQ7 129 S2_E1:0^1
1_RD_B_DQ38 206 S2_D0:2^1 1_RD_B_DQ6 128 S2_E0:7^1
1_RD_B_DQ37 201 S2_C2:1^1 1_RD_B_DQ5 123 S2_E0:3^1
1_RD_B_DQ36 200 S2_C2:4^1 1_RD_B_DQ4 122 S2_E0:2^1
1_RD_B_DQ35 88 S2_D0:1^1 1_RD_B_DQ3 10 S2_Q2^1
1_RD_B_DQ34 87 S2_D0:0^1 1_RD_B_DQ2 9 S2_E0:5^1
1_RD_B_DQ33 83 S2_C2:6^1 1_RD_B_DQ1 4 S2_E0:1^1
1_RD_B_DQ32 81 S2_C2:7^1 1_RD_B_DQ0 3 S2_E0:0^1
Table 3 – B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.)
Notes:
1. These signals are acquired from the second DIMM slot
2. All signals on this page are required for accurate post-processing of acquired data
3. The ‘S2’ in front of a TLA channel denotes Slave card #2 of the merged set
4. All signals on this page are stored in the TLA7BB4’s Prime memory and will not have a
MagniVu display value