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DDR3THIN-MN-XXX 4 Doc. Rev. 1.11
TABLE OF CONTENTS
1.0 OVERVIEW ........................................................................................................................... 9
1.1 General Information ............................................................................................................ 9
1.2 Software Package description..............................................................................................9
1.3 Eye size required ............................................................................................................... 11
2.0 SOFTWARE INSTALLATION........................................................................................... 11
3.0 CONNECTING to the NEX-DDR3INTR-THIN INTERPOSER ........................................ 12
3.1 General .............................................................................................................................. 12
3.2 B_DDR3D_2D Support..................................................................................................... 12
3.3 B_DDR3D_2G Support..................................................................................................... 12
3.4 B_DDR3D_3A Support..................................................................................................... 13
3.5 Short “LEASH” probes ..................................................................................................... 15
3.5.1 Samtec connector on the LEASH probe pins ............................................................ 16
3.5.2 LEASH probe to NEX-PRB1X/2X connection......................................................... 17
3.5.3 Alternate use of NEX-PRB1X or NEX-PRB2X probes............................................ 17
3.6 Slot Numbering............................................................................................................. 18
3.7 Display Groups not in Tables 1,2 or 3............................................................................... 39
4.0 CLOCK SELECTION .......................................................................................................... 40
4.1 B_DDR3D_2D Clocking Selections ................................................................................. 40
4.2 B_DDR3D_2G Clocking Selections ................................................................................. 41
4.3 B_DDR3D_3A Clocking Selections ................................................................................. 43
5.0 CONFIGURING FOR READ / WRITE DATA ACQUISITION........................................ 44
5.1 A Note About the Different Data Groups.......................................................................... 44
5.2 MagniVu Signals ............................................................................................................... 44
5.3 Adjusting Input Thresholds for Proper Data Acquisition.................................................. 53
5.4 DDR3 and DDR3SPA ....................................................................................................... 53
5.5 Selecting B_DDR3E_XX Read Data Sample Points ........................................................ 53
5.6 Selecting B_DDR3D_XX Write Data Sample Points....................................................... 54
5.7 B_DDR3D_XX Support Setup.......................................................................................... 55
5.8 Setting B_DDR3D_3A Read Data Sample Points ............................................................ 62
6.0 VIEWING DATA................................................................................................................. 63
6.1 Viewing B_DDR3D_XX Data .......................................................................................... 63
6.2 Viewing Raw DDR3 Data using B_DDR3D_XX Supports......................................... 66
6.3 B_DDR3D_2A / 3A Mnemonics Description................................................................... 66
6.4 B_DDR3D_2G Mnemonics Description........................................................................... 66
6.5 Viewing Timing Data on the TLA .................................................................................... 67
7.0 HINTS & TIPS ..................................................................................................................... 69
7.1 Symbolic Triggering on a Command using B_DDR3D_XX Supports............................. 69
7.3 Capturing MRS (Mode Register Set) Cycles .................................................................... 70
7.4 Clock Capture quality........................................................................................................ 71
7.5 Thresholds ......................................................................................................................... 72
APPENDIX A – How DDR Data is Clocked ............................................................................... 73
A.1 Background....................................................................................................................... 73
A.2 DDR Acquisition - General .............................................................................................. 73
A.3 B_DDR3D_2D / 2G / 3A Data Acquisition ..................................................................... 74
APPENDIX B - Considerations.................................................................................................... 75
B.1 NEX-DDR3INTR-THIN Bus Loading............................................................................. 75
B.2 DIMM connector location for best quality signal capture................................................ 75