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DDR3THIN-MN-XXX 5 Doc. Rev. 1.11
B.3 TLA7BB4 Module to module skew.................................................................................. 75
APPENDIX C – 240-pin DDR3 DIMM Pinout ........................................................................... 76
APPENDIX D –Data Flow Through the Probes (coax cable to channel) .................................... 78
APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0.................................................. 80
APPENDIX F – B_DDR3_2G Support Pinout, DIMM Slot 0 Auxiliary Signals ....................... 82
APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 ................................................. 84
APPENDIX H – Data Group / Data Byte / Strobe Cross-Reference............................................ 86
APPENDIX I – NEX-DDR3INTR-THIN Silkscreen................................................................... 87
APPENDIX J – Keep out area...................................................................................................... 88
APPENDIX K – Simulation Model.............................................................................................. 89
APPENDIX L - References .......................................................................................................... 90
APPENDIX M - Support .............................................................................................................. 91