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DDR3THIN-MN-XXX 40 Doc. Rev. 1.11
4.0 CLOCK SELECTION
4.1 B_DDR3D_2D Clocking Selections
There are two clocking option fields available when using the B_DDR3D_2D support package.
These select fields permit the user to setup the TLA acquisition as follows:
SDRAM Clocking: – Permits selecting the Clocking Mode to be used to acquire DDR3
data. It is important to note that the selection chosen will force unused Chip Selects and
CKE1 into inactive states. The field choices are:
S0#; Every Rising Edge (default) – Clocks data using every rising edge of DDR
Clock 0. Forces CKE1 low and S1-3# high. No Idle Cycle filtering is done.
S0# & S1#; Every Rising Edge – Clocks data using every rising edge of DDR
Clock 0. Forces S2-3# high. No Idle Cycle filtering is done.
S0-3#; Every Rising Edge – Clocks data using every rising edge of DDR Clock
0. No Idle Cycle filtering is done.
S0#; Total L <=5 – utilizes Selective Clocking to reduce acquisition of Idle bus
states. Forces CKE1 low and S1-3# high.
S0# & S1#; Total L <=5 - utilizes Selective Clocking to reduce acquisition of
Idle bus states. Forces S2-3# high.
S0-3#; Total L <=5 - utilizes Selective Clocking to reduce acquisition of Idle bus
states.
S0#; Total L <=6
S0# & S1#; Total L <=6
S0-3#; Total L <=6
.
.
.
S0#; Total L <=25
S0# & S1#; Total L <=25
S0-3#; Total L <=25
The above selections reduce the number of Idle cycles stored by the acquisition
card to provide optimum use of the acquisition memory. Data is stored whenever
RAS# or CAS# is asserted low along with a valid Chip Select. After every
assertion of CAS# (paired with a valid Chip Select) samples are taken during the
next X DDR Clock cycles to ensure that all valid memory cycles have been
acquired. The acquisition then pauses and waits for the next Command. If CAS#
and a Chip Select are asserted during these X clock cycles the count is reset. The
X-clock cycle value is determined by adding the maximum Burst Length of 8
clock cycles to the selected maximum Read Latency. So for a selected Total