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2 Instructions
2-304
CP1E CPU Unit Instructions Reference Manual(W483)
(3) Clearing/Retaining High-speed Counter Interrupts
Operand Specifications
Flags
Function
Depending on the value of N, CLI(691) clears the specified recorded I/O interrupts, sets the time before
execution of the first scheduled interrupt, or clears the specified recorded high-speed counter inter-
rupts.
(1) N = 102 to 107: Clearing Interrupt Inputs
CLI(691) clears a recorded interrupt input specified by N, when the corresponding bit of C is ON
and retains the recorded interrupt input when the corresponding bit is OFF.
If an I/O interrupt task is being executed and an interrupt input with a different interrupt number is
received, that interrupt number is recorded internally. The recorded I/O interrupts are executed
later in order of their priority (from the lowest number to the highest).
If you want to ignore interrupt inputs that are received while an interrupt task is being executed, use
CLI(691) to clear the recorded interrupts before they are executed.
Operand Contents
N
High-speed Counter Input
10: High-speed counter input 0
11: High-speed counter input 1
12: High-speed counter input 2
13: High-speed counter input 3
14: High-speed counter input 4
15: High-speed counter input 5 (Cannot be used in CP1E-E10D-)
C
Recorded Interrupt
0000 hex: Retain the recorded interrupt.
0001 hex: Clear the recorded interrupt.
Area
Word addresses Indirect DM addresses
Constants CF Pulse bits TR bits
CIO WR HR AR T C DM @DM *DM
N --- --- --- --- --- --- --- --- ---
OK --- --- ---
C OKOKOKOKOKOKOK OK OK
Name Label Operation
Error Flag P_ER • ON if N is not within the specified range.
• ON if C is not 0000 or 0001 hex (for I/O interrupts or high-speed counter interrupts).
• ON if C is not within the specified range of 10 to 9,999 decimal (000A to 270F hex) for scheduled
interrupts.
• OFF in all other cases.
Interrupt
input n
Internal
status
Recorded interrupt retained
Recorded interrupt cleared
Internal status
Interrupt input n