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Fibre Channel and Converged Network Adapters for VMware ESX/ESXi 4.0
User’s Guide
Glossary-4 FC0054607-00 A
ISL
Inter-switch link. The connection between
two switches using E_Ports.
ISP
Intelligent storage peripheral. QLogic
trademark and family of Fibre Channel and
SCSI controller chips that replace network
interface chips in network adapters,
servers, and storage.
LAN
Local area network. Network typically with
transmissions less than 5 km.
L_Port
Loop port. Does arbitrated loop functions
and protocols. NL_Ports and FL_Ports are
examples of loop-capable ports. See
E_Port, F_Port, FL_Port, G_Port, N_Port,
NL_Port.
LIP
Loop initialization process. The initializa-
tion process in an arbitrated loop that
occurs when the loop is powered up or a
new device is added. One function of a LIP
is to assign addresses. All data transmis-
sion on the loop is suspended during a LIP.
local area network
See LAN.
loop initialization process
See LIP.
logical unit number
See LUN.
loopback
Diagnostic tool that routes transmit data
through a loopback connector back to the
same adapter.
LUN
Logical unit number, a subdivision of a
SCSI target. It is the small integer handle
that differentiates an individual disk drive
or partition (volume) within a common
SCSI target device such as a disk array.
Technically, a LUN can be a single
physical disk drive, multiple physical disk
drives, or a portion (volume) of a single
physical disk drive. However, LUNs are
typically not entire disk drives but rather
virtual partitions (volumes) of a RAID set.
Using LUNs, the Fibre Channel host can
address multiple peripheral devices that
may share a common controller.
media
Physical-layer information carriers. Fibre
Channel supports several different
physical media: copper, multimode optical,
and single-mode optical. All Fibre Channel
protocols are supported on all media.
message signaled interrupts
See
MSI/MSI-X
Message signaled interrupts. An alternate
way of generating an interrupts with
special messages to allow PCI to emulate
a pin assertion or deassertion. Message
signaled interrupts allow the device to
write a small amount of data to a special
address in memory space. The chipset will
deliver the corresponding interrupt to a
CPU. MSI-X (defined in PCI 3.0) allows a
larger number of interrupts (up to 2048),
and gives each one a separate target
address and data word.