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Rev.1.02 Jul 01, 2005 page 52 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 7. Clock Generating Circuit
Under development
This document is under development and its contents are subject to change.
Table 7.7 Allowed Transition and Setting
State after transition
High-Speed Mode,
Low-Speed Low Power
PLL Operation
On-chip Oscillator
On-chip Oscillator
Stop Wait
Medium-Speed
Mode
(2)
Dissipation Mode
Mode (2) Mode
Low Power
Mode Mode
Mode
Dissipation Mode
High-Speed Mode,
(NOTE 8) (9)
(7)
-
(13)
(3)
(15)
-
(16)
(1)
(17)
Medium-Speed Mode
Low-Speed
(8) (11)
(1) (6)
---
(16)
(1)
(17)
Mode
(2)
Low Power
-
(10)
---
(16)
(1)
(17)
Dissipation Mode
PLL Operation
(12)
(3)
-- ----
Mode
(2)
On-chip Oscillator
(14)
(4)
---
(NOTE 8) (11)
(1)
(16)
(1)
(17)
Mode
On-chip Oscillator Low
----
(10) (NOTE 8) (16)
(1)
(17)
Power Dissipation Mode
Stop Mode
(18)
(5)
(18) (18)
-
(18)
(5)
(18)
(5)
-
Wait Mode
(18) (18) (18)
-
(18) (18)
-
Current state
Sub Clock Oscillating Sub Clock Turned Off
No
Divided Divided Divided Divided
No
Divided Divided Divided Divided
Division
by 2 by 4 by 8 by 16
Division
by 2 by 4 by 8 by 16
No Division
(4) (5) (7) (6) (1)
----
Divided by 2
(3) (5) (7) (6)
-
(1)
---
Divided by 4
(3) (4) (7) (6)
--
(1)
--
Divided by 8
(3) (4) (5) (6)
---
(1)
-
Divided by 16
(3) (4) (5) (7)
----
(1)
No Division
(2)
----
(4) (5) (7) (6)
Divided by 2
-
(2)
---
(3) (5) (7) (6)
Divided by 4
--
(2)
--
(3) (4) (7) (6)
Divided by 8
---
(2)
-
(3) (4) (5) (6)
Divided by 16
----
(2) (3) (4) (5) (7)
Sub Clock Oscillating
Sub Clock Turned Off
Setting Operation
(1) CM04=0 Sub clock turned off
(2) CM04=1 Sub clock oscillating
(
3) CM06=0 CPU clock no division
CM17=0 mode
CM16=0
(
4) CM06=0
CPU clock division by 2
CM17=0 mode
CM16=1
(
5) CM06=0
CPU clock division by 4
CM17=1 mode
CM16=0
(
6) CM06=0
CPU clock division by 16
CM17=1 mode
CM16=1
(7) CM06=1
CPU clock division by 8 mode
(8) CM07=0 Main clock, PLL clock
or on-chip oscillator
clock selected
(9) CM07=1 Sub clock selected
(10)
CM05=0 Main clock oscillating
(11)
CM05=1 Main clock turned off
(12)
PLC07=0 Main clock selected
CM11=0
(
13)
PLC07=1 PLL clock selected
CM11=1
(14)
CM21=0 Main clock or
PLL clock selected
(
15)
CM21=1 On-chip oscillator clock
selected
(16)
CM10=1 Transition to stop mode
(17)
WAIT Transition to wait mode
instruction
(18)
Hardware Exit stop mode or wait
interrupt mode
-: Cannot transit
NOTES:
1. Avoid making a transition when the CM20 bit = 1 (oscillation stop, re-
oscillation detection function enabled). Set the CM20 bit to “0” (oscillation
stop, re-oscillation detection function disabled) before transiting.
2. On-chip oscillator clock oscillates and stops in low-speed mode. In this
mode, the on-chip oscillator can be used as peripheral function clock. Sub
clock oscillates and stops in PLL operation mode. In this mode, sub clock
can be used as peripheral function clock.
3. PLL operation mode can only be entered from and changed to high-speed
mode.
4. Set the CM06 bit to “1” (division by 8 mode) before transiting from on-chip
oscillator mode to high- or medium-speed mode.
5. When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).
6. If the CM05 bit is set to “1” (main clock stop), then the CM06 bit is set to “1”
(division by 8 mode).
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or sub
clock oscillation turned on or off) are shown in the table below.
CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM11, CM16, CM17: Bits in CM1 register
CM20, CM21 : Bits in CM2 register
PLC07 : Bit in PLC0 register
9. ( ):setting method. See right table.