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Rev.1.02 Jul 01, 2005 page 56 of 314
REJ09B0126-0102
M16C/6N Group (M16C/6NL, M16C/6NN) 9. Interrupt
Under development
This document is under development and its contents are subject to change.
Figure 9.1 Interrupts
• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-Maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
Interrupt
Software
(Non-maskable interrupt)
Hardware
Special
(Non-maskable interrupt)
Peripheral function
(1)
(Maskable interrupt)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
_______
NMI
________
DBC
(2)
Oscillation stop and re-oscillation detection
Watchdog timer
Single step
(2)
Address match
NOTES:
1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt.
2. Do not normally use this interrupt because it is provided exclusively for use by development
support tools.
9. Interrupt
9.1 Type of Interrupts
Figure 9.1 shows the types of interrupts.