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Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i 109 Revision 1.22 (09-25-08)
DATASHEET
4.3.6 DMA Controller Status Register (DMAC_STATUS)
This register contains all of the status bits that the DMAC reports to the Host system. Most of the fields
in this register will cause an interrupt. Status can be checked as part of an interrupt service routine, or
by polling. DMAC interrupts can be masked in the DMAC_INTR_ENA register.
Offset: 0014h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:23 RESERVED RO -
22:20 Transmit Process State (TS)
This Read-Only field indicates the state of the transmit process. This field
does not generate an interrupt. The TS field is encoded as follows:
RO 000b
19:17 Receive Process State (RS)
This Read-Only field indicates the state of the receive process. This field
does not generate an interrupt. The RS field is encoded as follows:
RO 000b
16 Normal Interrupt Summary (NIS)
This bit is the logical OR of other bits within this register. Only unmasked
bits affect this register. Below is the list of bits:
DMAC_STATUS[0]: Transmit interrupt (TI)
DMAC_STATUS[2]: Transmit buffer unavailable (TU)
DMAC_STATUS[6]: Receive interrupt (RI)
R/WC 0b
15 Abnormal Interrupt Summary (AIS)
This bit is the logical OR of other bits within this register. Only unmasked
bits affect this register. Below is the list of bits:
DMAC_STATUS[1]: Transmit process stopped (TPS)
DMAC_STATUS[7]: Receive buffer unavailable (RU)
DMAC_STATUS[8]: Receive process stopped (RPS)
R/WC 0b
STATE DESCRIPTION
000 Stopped - Reset or Stop command issued
001 Running - Fetching the transmit descriptor
010 Running - Waiting for the end of transmission
011 Running - Reading the data from memory and queuing into TX FIFO
100 RESERVED
101 RESERVED
110 Suspended - Unavailable transmit descriptor
111 Running - Closing the transmit descriptor
STATE DESCRIPTION
000 Stopped - Reset or Stop receive command
001 Running - Fetching the receive descriptor
010 Running - Checking for end of receive packet before prefetch of next
descriptor
011 Running - Waiting for receive packet
100 Suspended - Unavailable receive descriptor
101 Running - Closing receive descriptor
110 Running - Flushing the current frame from the receive buffer because
of unavailable receive buffer
111 Running - Queuing the receive frame from the receive buffer into the
Host memory