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Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
SMSC LAN9420/LAN9420i 163 Revision 1.22 (09-25-08)
DATASHEET
5.7 PCI I/O Timing
The following specifies the PCI I/O requirements for LAN9420/LAN9420i:
Note: Input test is done with 0.1*VDD33IO overdrive. V
max
specifies the maximum peak-to-peak
waveform allowed for testing input timing.
Figure 5.3 PCI I/O Timing
Table 5.10 PCI I/O Timing Measurement Conditions
SYMBOL VALUE UNITS
V
th
0.6*VDD33IO V
V
tl
0.2*VDD33IO V
V
test
0.4*VDD33IO V
V
trise
0.285*VDD33IO V
V
tfall
0.615*VDD33IO V
V
max
0.4*VDD33IO V
Input Signal Edge Rate
1V/ns
PCICLK
TRI-STATE PCI
OUTPUTS
PCI OUTPUTS
t
val
t
on
t
off
t
su
t
h
PCI INPUTS
V
test
V
trise,
V
tfall
V
test
V
th
V
tl
V
th
V
tl
V
max