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Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface
Datasheet
Revision 1.22 (09-25-08) 88 SMSC LAN9420/LAN9420i
DATASHEET
4.2.2 Interrupt Control Register (INT_CTL)
Interrupts are enabled/disabled through this register. Refer to Section 3.3.1, "Interrupt Controller," on
page 28 for more information on the Interrupt Controller.
Note: The DMAC interrupt (DMAC_INT) is enabled through the DCSR.
Offset: 00C4h Size: 32 bits
BITS DESCRIPTION TYPE DEFAULT
31:16 RESERVED RO -
15 Software Interrupt Enable (SW_INT_EN)
On a transition from low to high, this register bit triggers the software
interrupt.
R/W 0b
14 RESERVED RO -
13 Master Bus Error Interrupt Enable (MBERR_INT_EN)
When set high, the Master Bus Error is enabled to generate an interrupt.
R/W 0b
12 Slave Bus Error Interrupt Enable (SBERR_INT_EN)
When set high, the Slave Bus Error is enabled to generate an interrupt.
R/W 0b
11:7 RESERVED RO -
6:4 GPIO [2:0] (GPIOx_INT_EN)
When set high the GPIOx are enabled as interrupt sources.
R/W 000b
3 GP Timer Interrupt Enable (GPT_INT_EN)
When set high the General Purpose Timer is enabled as an interrupt
source.
R/W 0b
2 PHY Interrupt Enable (PHY_INT_EN)
When set high, the PHY interrupt is enabled as an interrupt source.
R/W 0b
1 Wake Event Interrupt Enable (WAKE_INT_EN)
When set high, wake event detection is enabled as an interrupt source.
R/W 0b
0 RESERVED RO -