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MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
oscillator and system clock (continued)
DIVA
XIN
LFXT1 OSCILLATOR
ACLK
O
SC
Off XTS
/1, /2, /4, /8
2
DIVM
/1, /2, /4, /8, Off
22
SELM CPUOff
Auxiliary Clock
MCLK
Main System Clock
DIVS
/1, /2, /4, /8, Off
2
SELS SCG1
SMCLK
Subsystem Clock
XOUT
SMCLKGEN
LFXT1CLK
MCLKGEN
ACLKGEN
DCOMOD
DCOCLK
Digital Controlled Oscillator (DCO)
+
Modulator (MOD)
DC
Generator
53
DCO MODR
sel
SCG0
DCOR
The DCO-Generator is connected to pin P2.5/Rosc if DCOR control bit is set.
The port pin P2.5/Rosc is selected if DCOR control bit is reset (initial state).
P2.5
V
CC
V
CC
0
1
P2.5/Rosc
3
2
0
1
DCGEN
0,1
Figure 3. Clock Signals
Two clock sources, LFXT1CLK and DCOCLK, can be used to drive the MSP430 system. The LFXT1CLK is
generated from the LFXT1 crystal oscillator. The LFXT1 crystal oscillator can operate in three modes—low
frequency (LF), moderate frequency (XT1), and external input mode. The LFXT1 crystal oscillator may be
switched off when it is not in use.
DCOCLK is generated from the DCO. The nominal DCO frequency is defined by the dc generator and can be
set by one external resistor, or can be set to one of eight values with integrated resistors. Additional adjustments
and modulations of DCOCLK are possible by software manipulation of registers in the DCO module. DCOCLK
is stopped automatically when it is not used by the CPU or peripheral modules. The dc generator can be shut
down with the SCG0 bit to realize additional power savings when DCOCLK is not in use.
NOTE:
The system clock generator always starts with the DCOCLK selected for MCLK (CPU clock) to
ensure proper start of program execution. The software defines the final system clock generation
through control bit manipulation.
digital I/O
There are two eight-bit I/O ports, port P1 and port P2 – implemented (11x1 parts only have six port P2 I/O signals
available on external pins). Both ports, P1 and P2, have seven control registers to give maximum flexibility of
digital input/output to the application:
• All individual I/O bits are programmable independently.
• Any combination of input, output, and interrupt conditions is possible.
• Interrupt processing of external events is fully implemented for all eight bits of port P1 and for six bits of
port P2.
• Read/write access to all registers with all instructions