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TPS56xx Functions
2-10
An alternate current sensing scheme is to insert a current sense resistor in
series with the drain of Q1. Higher accuracy may be obtained at the expense
of lower efficiency.
2.1.7 Overvoltage Protection
If V
O
exceeds Vref by 15%, a fault latch is set and the output gate drivers are
turned off. The latch remains set until VCC (pin 15) goes below the
undervoltage lockout value.
In addition to the standard OVP protection, the LODRV circuit protects the
processor against overvoltages due to a short across the high-side power
MOSFET. External components to sense an overvoltage condition are
required to use this feature. When a shorted high-side MOSFET occurs, the
low-side MOSFET is used as a crowbar. LODRV is pulled low and the low-side
MOSFET is turned on, overriding all control signals inside the controller. The
crowbar action shorts the input supply to ground through the faulted high-side
MOSFET. A fuse in series with V
I
must be added to disconnect the
short-circuit.
2.1.8 Power Good
The power-good circuit monitors for an undervoltage condition on V
O
. If V
O
drops below 93% of VREF, then the PWRGD output is pulled low. PWRGD is
an open-drain output and needs a pullup resistor.
2.1.9 Bias
Analog BIAS (pin 9), the output of the internal analog bias regulator, is
designed to provide a quiet bias supply for the internal TPS56xx circuitry.
External loads should not be driven by the bias regulator. A 1-µF capacitor,
C22, is connected from BIAS to ANAGND.
2.1.10 Gate Drivers
The gate drivers drive large capacitive loads quickly and efficiently. Figure 2–4
is a block diagram of the drivers. The output stage of the drivers consists of
bipolar and MOS transistors in parallel. The bipolar transistors provide the
majority of the 2-A drive current. The driver outputs get pulled to ground
(during sinking) or to the supply rail (during sourcing) by the MOS transistors.
If the MOS transistors were not in the design, the voltage level on the driver
outputs could only be driven to the saturation voltage level of the bipolar
transistors. This could be a serious limitation, especially if logic-level power
MOSFETs are used in the power stage, resulting in shoot-through current
through the power MOSFETs.