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External Component Selection
2-15
Design Procedure
performance in response to fast load transients encountered when supplying
power to current- and next-generation microprocessors. A secondary
consideration is the switching frequency resulting from the output filter
component values. This section discusses important considerations when
selecting/designing the output filter elements. A detailed analysis of the output
voltage ripple characteristics is also presented, resulting in an expression for
predicting the power supply switching frequency.
2.2.3.1 Output Capacitance
Normally, the output capacitor is selected to limit ripple voltage to the level
required by the specification, but in a hysteretic regulator, such as this one, the
TPS55xx essentially determines the output voltage ripple. The output ripple
is previously chosen to be less than 2% of V
O
and is relatively independent of
the output capacitor characteristics. Since output voltage ripple is set by the
comparator hysteresis band, the output capacitor is chosen to provide
satisfactory response to fast load transients.
To show the importance of the output capacitor characteristics, consider the
following: This example circuit is designed for a worst case load step of no load
(0 Amps) to full load (6 Amps) with a slew rate of 30 A/µs. For a transient of
this slew rate, the output filter alone controls the initial output voltage deviation.
Further examination shows that the output filter inductor current changes little
during the load transient. Therefore, for fast load transients, the output
capacitor characteristics dominate the output filter performance. In this
design, the output capacitor’s ESR (equivalent series resistance) and ESL
(equivalent series inductance) are the parameters that are most critical.
To calculate the ESR requirement, assume that all the load transient current
is supplied by the output capacitor. Also assume that the output voltage
change due to the capacitor’s capacitance is much smaller than the voltage
change due to the ESR, and that the capacitor’s ESL is negligible. In most
practical applications, these assumptions are reasonable and they greatly
simplify calculations. The ESR required to limit output voltage change to
100 mV due to a 6 amp load step is:
ESR
v
D
V
O
D
I
O
+
100
mV
6
A
+ 16.7
m
W
The required level of ESR requires a large amount of capacitance. For this
design, four Sanyo POSCAP type electrolytic capacitors connected in parallel
are selected. These capacitors are a good compromise between
performance, cost, and board area requirements. The particular part used is
an 150-µF, 4-V capacitor with a specified maximum ESR of 45 mΩ, giving a
total maximum ESR of 11.25 mΩ. These capacitors are C10, C11, C12, and
C13 in Figure 1–3. For good design practice, C14, a 10-µF ceramic capacitor,
is placed in parallel with C10–C13. Ceramic capacitors are very effective for
suppressing high frequency switching spikes and reducing the effects of the
ESL of C10–C13.
To summarize, the output capacitance must be selected to provide a
sufficiently low ESR. The capacitor(s) must have an adequate voltage rating