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9.2.3DM642VirtualI
2
CRegisterDetails
Quad 1 Quad 2
Quad 3 Quad 4
Decoder1
Scaled
Decoder2
Unscaled
Decoder2
Unscaled
Decoder4
Scaled
ProgrammingtheTMS320DM642
Table10.Decoder1Register
Address00h
Default02h
76543210
Capture
ReservedPositionCaptureSize
Enable
CaptureSizeBit2Bit1Bit0
Unscaled000
QSIF–176×120001
SIF–352×240(1/4NTSC)
010
(default)
QCIF–176×144011
CIF–352×288(1/4PAL)100
QVGA–320×240101
VGA–640×480110
Reserved111
CaptureEnableBit3
Disable(default)0
Enable1
PositionBit5Bit4
Quadrant1(default)00
Quadrant201
Quadrant310
Quadrant411
Scaledcapturesizesalwaystakepriorityoverunscaledcapturesizes.
DecoderprioritiesarealwayssuchthatDecoder1isthehighestpriority,Decoder2isthesecondhighest,
etc.
Forexample,ifDecoders1and4arescaledto1/4sizeandDecoders2and3areunscaled,thisdisplay
results:
28TVP5154EVMUser'sGuideSLEU069A–February2006–RevisedJuly2006
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