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36 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 2: Core Architecture
R
Dynamic Switching Signal Pinout
Table 2-6 describes the signals present when the optional Dynamic Switching mode
(between 1000BASE-X and SGMII standards) is selected. In this case, the MDIO (Table 2-3)
and RocketIO transceiver (Table 2-7) interfaces are always present.
Physical Side Interface
1000BASE-X PCS with PMA Using RocketIO Transceiver Signal Pinout
(Optional)
Table 2-7 describes the optional interface to the RocketIO transceiver. The core is connected
to a RocketIO transceiver in the appropriate HDL example design delivered with the core.
For more information, see:
• Chapter 7, “1000BASE-X with RocketIO Transceivers”
• Chapter 8, “SGMII / Dynamic Standards Switching with RocketIO Transceivers”
Table 2-6: Optional Dynamic Standard Switching Signals
Signal Direction Description
link_timer_basex[8:0]
1
1. Clock domain is userclk2.
Input Used to configure the duration of the Auto-
Negotiation Link Timer period when performing
the 1000BASE-X standard. The duration of this
timer is set to the binary number input into this port
multiplied by 4096 clock periods of the 125 MHz
reference clock (8 ns). It is expected that this signal
will be tied off to a logical value.
link_timer_sgmii[8:0]
1
Input Used to configure the duration of the Auto-
Negotiation Link Timer period when performing
the SGMII standard. The duration of this timer is set
to the binary number input into this port multiplied
by 4096 clock periods of the 125 MHz reference
clock (8 ns). It is expected that this signal will be tied
off to a logical value.
basex_or_sgmii
1
Input Used as the reset default to select the standard. It is
expected that this signal will be tied off to a logical
value.
‘0’ signals that the core will come out of reset
operating as 1000BASE-X.
‘1’ signals that the core will come out of reset
operating as SGMII.
Note: The standard can be set following reset
through the MDIO Management.