Architecture
Table2.EMACandMDIOSignalsforGMIIInterface(continued)
SignalTypeDescription
MCRSICarriersense(MCRS).TheMCRSpinisassertedbythePHYwhenthenetworkisnotidleineither
transmitorreceive.Thepinisde-assertedwhenbothtransmitandreceiveareidle.Thissignalisnot
necessarilysynchronoustoMTCLKnorMRCLK.Thispinisusedinhalf-duplexoperationonly.
MRCLKIReceiveclock(MRCLK).Thereceiveclockisacontinuousclockthatprovidesthetimingreference
forreceiveoperations.TheMRXD,MRXDV,andMRXERsignalsaretiedtothisclock.Theclockis
generatedbythePHYandis2.5MHZat10Mbpsoperation,25MHZat100Mbpsoperationand
125MHZat1000Mbpsoperation.
MRXD[7-0]IReceivedata(MRXD).Thereceivedatapinsareacollectionof8datasignalscomprising8bitsof
data.MRDX0istheleast-significantbit(LSB).ThesignalsaresynchronizedbyMRCLKandvalid
onlywhenMRXDVisasserted.
MRXDVIReceivedatavalid(MRXDV).ThereceivedatavalidsignalindicatesthattheMRXDpinsare
generatingnibbledataforusebytheEMAC.ItisdrivensynchronouslytoMRCLK.
MRXERIReceiveerror(MRXER).ThereceiveerrorsignalisassertedforoneormoreMRCLKperiodsto
indicatethatanerrorwasdetectedinthereceivedframe.Thisismeaningfulonlyduringdata
receptionwhenMRXDVisactive.
MDCLKOManagementdataclock(MDCLK).TheMDIOdataclockissourcedbytheMDIOmoduleonthe
system.ItisusedtosynchronizeMDIOdataaccessoperationsdoneontheMDIOpin.The
frequencyofthisclockiscontrolledbytheCLKDIVbitsintheMDIOcontrolregister(CONTROL).
MDIOI/OManagementdatainputoutput(MDIO).TheMDIOpindrivesPHYmanagementdataintoandoutof
thePHYbywayofanaccessframeconsistingofstartofframe,read/writeindication,PHYaddress,
registeraddress,anddatabitcycles.TheMDIOpinactsasanoutputforeverythingexceptthedata
bitcycles,whenthepinactsasaninputforreadoperations.
18EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)SPRUEQ6–December2007
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