2.9MediaIndependentInterface(MII)
2.9.1DataReception
2.9.1.1ReceiveControl
2.9.1.2ReceiveInter-FrameInterval
2.9.1.3ReceiveFlowControl
Architecture
ThefollowingsectionsdiscusstheoperationoftheMediaIndependentInterface(MII)in10Mbpsand
100Mbpsmode.AnIEEE802.3compliantEthernetMACcontrolstheinterface.
DatareceivedfromthePHYisinterpretedandoutputtotheEMACreceiveFIFO.Interpretationinvolves
detectionandremovalofthepreambleandstart-of-framedelimiter,extractionoftheaddressandframe
length,datahandling,errorcheckingandreporting,cyclicredundancychecking(CRC),andstatistics
controlsignalgeneration.AddressdetectionandframefilteringisperformedoutsidetheMIIinterface.
The802.3standardrequiresaninterpacketgap(IPG),whichis24MIIclocks(96bittimes).However,the
EMACcantolerateareducedIPG(2MIIclocksor8bittimes)withacorrectpreambleandstartframe
delimiter.Thisintervalbetweenframesmustcomprise(inthefollowingorder):
1.AnInterpacketGap(IPG).
2.A7-bytepreamble(allbytes55h).
3.A1-bytestartofframedelimiter(5DH).
Whenenabledandtriggered,receiveflowcontrolisinitiatedtolimittheEMACfromfurtherframe
reception.TwoformsofreceiveflowcontrolareimplementedontheDM646xDMSoC:
•Receivebufferflowcontrol
•ReceiveFIFOflowcontrol
Whenenabledandtriggered,receivebufferflowcontrolpreventsfurtherframereceptionbasedonthe
numberoffreebuffersavailable.Receivebufferflowcontrolissuesflowcontrolcollisionsinhalf-duplex
modeandIEEE802.3Xpauseframesforfull-duplexmode.Receivebufferflowcontrolistriggeredwhen
thenumberoffreebuffersinanyenabledreceivechannelfreebuffercountregister(RXnFREEBUFFER)
islessthanorequaltothereceivechannelflowcontrolthresholdregister(RXnFLOWTHRESH)value.
ReceiveflowcontrolisindependentofreceiveQOS,exceptthatbothusethefreebuffervalues.
Whenenabledandtriggered,receiveFIFOflowcontrolpreventsfurtherframereceptionbasedonthe
numberofcellscurrentlyinthereceiveFIFO.ReceiveFIFOflowcontrolmaybeenabledonlyin
full-duplexmode(FULLDUPLEXbitissetintheintheMACcontrolregister,MACCONTROL).Receive
flowcontrolpreventsreceptionofframesontheportuntilallofthetriggeringconditionsclear,atwhich
timeframesmayagainbereceivedbytheport.
ReceiveFIFOflowcontrolistriggeredwhentheoccupancyoftheFIFOisgreaterthanorequaltothe
RXFIFOFLOWTHRESHvalueintheFIFOcontrolregister(FIFOCONTROL).TheRXFIFOFLOWTHRESH
valuemustbegreaterthanorequalto1handlessthanorequalto42h(decimal66).The
RXFIFOFLOWTHRESHresetvalueis2h.
ReceiveflowcontrolisenabledbytheRXBUFFERFLOWENbitandtheRXFIFOFLOWENbitin
MACCONTROL.TheFULLDUPLEXbitinMACCONTROLconfigurestheEMACforcollisionor
IEEE802.3Xflowcontrol.
SPRUEQ6–December2007EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)41
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