Architecture
Example4.EMACControlModuleInitializationCode
Uint32tmpval;
/*DisablealltheEMAC/MDIOinterruptsinthecontrolmodule*/
EmacControlRegs->CONTROL.C_RX_EN=0;
EmacControlRegs->CONTROL.C_TX_EN=0;
EmacControlRegs->CONTROL.C_RX_THRESH_EN=0;
EmacControlRegs->CONTROL.C_MISC_EN=0;
/*Waitabout100cycles*/
for(I=0;i<5;I++)
tmpval=ECTL_REGS->EWCTL;
#ifdefINTT_PACING
/*SetthecontrolrelatedtopacingofTXandRXinterrupts*/
EmacControlRegs->INTR_COUNT->C_RX_IMAX=0x4;//4RXintt/ms
EmacControlRegs->INTR_COUNT->C_TX_IMAX=0x4;//4TXintt/ms
EmacControlRegs->INT_CONTROL=0x30000;//bit16,bit17forenablingTXandRxinttpacing.
EmacControlRegs->INT_CONTROL|=0x258;//600clocksof150MHzin4ustime
#endif
/*InitializeMDIOandEMACModule*/
[Discussedlaterinthisdocument]
/*EnablealltheEMAC/MDIOinterruptsinthecontrolmodule*/
EmacControlRegs->CONTROL.C_RX_EN=0xff;
EmacControlRegs->CONTROL.C_TX_EN=0xff;
EmacControlRegs->CONTROL.C_RX_THRESH_EN=0xff;
EmacControlRegs->CONTROL.C_MISC_EN=0xf;
SPRUEQ6–December2007EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)53
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