2.13TransferNodePriority
2.14ResetConsiderations
2.14.1SoftwareResetConsiderations
Architecture
Receiveoverrunispreventedifthereceivememorycelllatencyislessthanthetimerequiredtotransmita
64-bytecellonthewire(0.512msin1Gbpsmode,5.12msin100Mbpsmode,or51.2msin10Mbps
mode).Thelatencytimeincludesanyrequiredbufferdescriptorreadsforthecelldata.
LatencytodescriptorRAMislowbecauseRAMislocaltotheEMAC,asitispartoftheEMACcontrol
module.
TheDM646xdevicecontainsachip-levelregister,masterpriorityregister(MSTPRI),thatisusedtoset
thepriorityofthetransfernodeusedinissuingmemorytransferrequeststosystemmemory.
AlthoughtheEMAChasinternalFIFOstohelpalleviatememorytransferarbitrationproblems,theaverage
transferrateofdatareadandwrittenbytheEMACtointernalorexternalprocessormemorymustbeat
leastthatoftheEthernetwirerate.Inaddition,theinternalFIFOsystemcannotwithstandasingle
memorylatencyeventgreaterthanthetimeittakestofilloremptyaTXCELLTHRESHnumberofinternal
64-byteFIFOcells.
For100Mbpsoperation,theserestrictionstranslateintothefollowingrules:
•Theshort-termaverage,each64-bytememoryread/writerequestfromtheEMACmustbeservicedin
nomorethan5.12µs.
•Anysinglelatencyeventinrequestservicingcanbenolongerthan(5.12×TXCELLTHRESH)µs.
Bits0-2ofthesecondchip-levelmasterpriorityregister(MSTPRI1)areusedtosetthetransfernode
prioritywithintheSwitchedCentralResource(SCR5)fortheEMACmasterperipheral.
Avalueof000bhasthehighestpriority,while111bhasthelowestpriority.Thedefaultpriorityassignedto
theEMACis100b.Itisimportanttohaveabalancebetweenallperipherals.Inmostcases,thedefault
prioritieswillnotneedadjustment.Formoreinformationonthemasterperipheralspriorities,seethe
device-specificdatamanual.
PeripheralclockandresetcontrolisdonethroughthePowerandSleepController(PSC)moduleincluded
withthedevice.FormoreonhowtheEMAC,MDIO,andEMACcontrolmodulearedisabledorplacedin
resetatruntimefromtheregisterslocatedinthePSCmodule,seeSection2.17.
Note:Forproperoperation,boththeEMACandEMACcontrolmodulemustberesetinthe
followingsequence.First,thesoftresetoftheEMACmoduleshouldbecommanded.After
theresettakeseffect(verifiedbyreadingbackSOFTRESET),thesoftresetoftheEMAC
controlmoduleshouldbecommanded.
WithintheperipheraltherearetwocontrolstoseparatelyresettheEMACandtheEMACcontrolmodule.
•TheEMACcomponentoftheEthernetMACperipheralcanbeplacedinaresetstatebywritingtothe
softresetregister(SOFTRESET).Writinga1totheSOFTRESETbit,causestheEMAClogictobe
resetandtheregistervaluestobesettotheirdefaultvalues.Softwareresetoccurswhenthereceive
andtransmitDMAcontrollersareinanidlestatetoavoidlockinguptheconfigurationbus;itisthe
responsibilityofthesoftwaretoverifythattherearenopendingframestobetransferred.Afterwritinga
1totheSOFTRESETbit,itmaybepolledtodetermineiftheresethasoccurred.Ifa1isread,the
resethasnotyetoccurred;ifa0isread,thenaresethasoccurred.
•TheEMACcontrolmodulesoftwareresetregister(CMSOFTRESET)isusedtoplacetheEMAC
controlmodulelogicinsoftreset.Thisresetsthecontrollogic,theEMACregisters,aswellas,the
EMACcontrolmodule8KBinternalmemorythatmaybeusedforstoringthetransferdescriptors.
Afterasoftwareresetoperation,alltheEMACregistersneedtobereinitializedforproperdata
transmission.
UnliketheEMACmodule,theMDIOandEMACcontrolmodulescannotbeplacedinresetfromaregister
insidetheirmemorymap.
SPRUEQ6–December2007EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)51
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