2.14.2HardwareResetConsiderations
2.15Initialization
2.15.1EnablingtheEMAC/MDIOPeripheral
2.15.2EMACControlModuleInitialization
Architecture
Whenahardwareresetoccurs,theEMACperipheralhasitsregistervaluesresetandallthecomponents
returntotheirdefaultstate.Afterthehardwarereset,theEMACneedstobeinitializedbeforebeingable
toresumeitsdatatransmission,asdescribedinSection2.15.
Ahardwareresetistheonlymeansofrecoveringfromtheerrorinterrupts(HOSTPEND),whichare
triggeredbyerrorsinpacketbufferdescriptors.Beforedoingahardwarereset,youshouldinspectthe
errorcodesintheMACstatusregister(MACSTATUS)thatgivesinformationaboutthetypeofsoftware
errorthatneedstobecorrected.Fordetailedinformationonerrorinterrupts,seeSection2.16.1.5.
Whenthedeviceispoweredon,theEMACperipheralisinadisabledstate.BeforeanyEMACspecific
initializationcantakeplace,theEMACneedstobeenabled;otherwise,itsregisterscannotbewrittenand
thereadswillallreturnavalueofzero.
TheEMAC/MDIOisenabledthroughthePowerandSleepController(PSC)registers.Forinformationon
howtoenabletheEMACperipheralfromthePSC,seetheTMS320DM646xDMSoCARMSubsystem
ReferenceGuide(SPRUEP9).
Whenfirstenabled,theEMACperipheralregistersaresettotheirdefaultvalues.Afterenablingthe
peripheral,youmayproceedwiththemodulespecificinitialization.
TheEMACcontrolmoduleisusedforglobalinterruptenable,andtopaceback-to-backinterruptsusing
aninterruptretriggercountbasedontheperipheralclock(PLL1/6).Thereisalsoan8KblockofRAMlocal
totheEMACthatisusedtoholdpacketbufferdescriptors.
NotethatalthoughtheEMACcontrolmoduleandtheEMACmodulehaveslightlydifferentfunctions,in
practice,thetypeofmaintenanceperformedontheEMACcontrolmoduleismorecommonlyconducted
fromtheEMACmodulesoftware(asopposedtotheMDIOmodule).
TheinitializationoftheEMACcontrolmoduleconsistsoftwoparts:
1.ConfigurationoftheinterrupttotheCPU.
2.InitializationoftheEMACcontrolmodule:
•Settingtheregistersrelatedtointerruptpacing.ThisappliesonlytoRXPulseandTXPulse
interrupts.Bydefault,interruptspacingisdisabled.IfpacingisenabledbyprogrammingtheEMAC
controlmoduleinterruptcontrolregister(CMINTCTRL),thentheCMTXINTMAXand
CMRXINTMAXregistershavetobeprogrammed,toindicatethemaximumnumberofTX_PULSE
andRX_PULSEinterruptspermillisecond.
•InitializingtheEMACandMDIOmodules.
•EnablinginterruptsintheEMACcontrolmoduleusingtheEMACcontrolmoduleinterruptcontrol
registers(CMRXTHRESHINTEN,CMRXINTEN,CMTXINTEN,andCMMISCINTEN).
Whenusingtheregister-levelCSL,thecodetoperformtheactionsassociatedwiththesecondpartmay
appearasinExample4.
TheprocessofmappingtheEMACinterruptstooneoftheCPU’sinterruptsisdoneusingtheARM
interruptcontroller.OncetheinterruptismappedtoaCPUinterrupt,generalmaskingandunmaskingof
theinterrupt(tocontrolreentrancy)shouldbedoneatthechiplevelbymanipulatingtheinterruptenable
mask.
52EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)SPRUEQ6–December2007
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