5EthernetMediaAccessController(EMAC)Registers
EthernetMediaAccessController(EMAC)Registers
Table39liststhememory-mappedregistersfortheEMAC.Seethedevice-specificdatamanualforthe
memoryaddressoftheseregisters.
Table39.EthernetMediaAccessController(EMAC)Registers
OffsetAcronymRegisterDescriptionSection
0hTXIDVERTransmitIdentificationandVersionRegisterSection5.1
4hTXCONTROLTransmitControlRegisterSection5.2
8hTXTEARDOWNTransmitTeardownRegisterSection5.3
10hRXIDVERReceiveIdentificationandVersionRegisterSection5.4
14hRXCONTROLReceiveControlRegisterSection5.5
18hRXTEARDOWNReceiveTeardownRegisterSection5.6
80hTXINTSTATRAWTransmitInterruptStatus(Unmasked)RegisterSection5.7
84hTXINTSTATMASKEDTransmitInterruptStatus(Masked)RegisterSection5.8
88hTXINTMASKSETTransmitInterruptMaskSetRegisterSection5.9
8ChTXINTMASKCLEARTransmitInterruptClearRegisterSection5.10
90hMACINVECTORMACInputVectorRegisterSection5.11
94hMACEOIVECTORMACEndofInterruptVectorRegisterSection5.12
A0hRXINTSTATRAWReceiveInterruptStatus(Unmasked)RegisterSection5.13
A4hRXINTSTATMASKEDReceiveInterruptStatus(Masked)RegisterSection5.14
A8hRXINTMASKSETReceiveInterruptMaskSetRegisterSection5.15
AChRXINTMASKCLEARReceiveInterruptMaskClearRegisterSection5.16
B0hMACINTSTATRAWMACInterruptStatus(Unmasked)RegisterSection5.17
B4hMACINTSTATMASKEDMACInterruptStatus(Masked)RegisterSection5.18
B8hMACINTMASKSETMACInterruptMaskSetRegisterSection5.19
BChMACINTMASKCLEARMACInterruptMaskClearRegisterSection5.20
100hRXMBPENABLEReceiveMulticast/Broadcast/PromiscuousChannelEnableRegisterSection5.21
104hRXUNICASTSETReceiveUnicastEnableSetRegisterSection5.22
108hRXUNICASTCLEARReceiveUnicastClearRegisterSection5.23
10ChRXMAXLENReceiveMaximumLengthRegisterSection5.24
110hRXBUFFEROFFSETReceiveBufferOffsetRegisterSection5.25
114hRXFILTERLOWTHRESHReceiveFilterLowPriorityFrameThresholdRegisterSection5.26
120hRX0FLOWTHRESHReceiveChannel0FlowControlThresholdRegisterSection5.27
124hRX1FLOWTHRESHReceiveChannel1FlowControlThresholdRegisterSection5.27
128hRX2FLOWTHRESHReceiveChannel2FlowControlThresholdRegisterSection5.27
12ChRX3FLOWTHRESHReceiveChannel3FlowControlThresholdRegisterSection5.27
130hRX4FLOWTHRESHReceiveChannel4FlowControlThresholdRegisterSection5.27
134hRX5FLOWTHRESHReceiveChannel5FlowControlThresholdRegisterSection5.27
138hRX6FLOWTHRESHReceiveChannel6FlowControlThresholdRegisterSection5.27
13ChRX7FLOWTHRESHReceiveChannel7FlowControlThresholdRegisterSection5.27
140hRX0FREEBUFFERReceiveChannel0FreeBufferCountRegisterSection5.28
144hRX1FREEBUFFERReceiveChannel1FreeBufferCountRegisterSection5.28
148hRX2FREEBUFFERReceiveChannel2FreeBufferCountRegisterSection5.28
14ChRX3FREEBUFFERReceiveChannel3FreeBufferCountRegisterSection5.28
150hRX4FREEBUFFERReceiveChannel4FreeBufferCountRegisterSection5.28
154hRX5FREEBUFFERReceiveChannel5FreeBufferCountRegisterSection5.28
158hRX6FREEBUFFERReceiveChannel6FreeBufferCountRegisterSection5.28
15ChRX7FREEBUFFERReceiveChannel7FreeBufferCountRegisterSection5.28
160hMACCONTROLMACControlRegisterSection5.29
84EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)SPRUEQ6–December2007
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