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AMX 68000 Target Guide
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3. The Processor Interrupt System
3.1 Operation
The M68000 classifies all internal and external sources of interruption as exceptions.
The processor automatically determines the cause of the exception and then branches
indirectly through entries in the processor Exception Vector Table to an appropriate
exception specific procedure.
The particular procedures which service internal or external device interrupt requests are
called Interrupt Service Procedures. All other procedures are referred to as exception
service procedures.
Upon entry to any Interrupt Service Procedure or exception service procedure the
processor state is determined by the particular exception.
Device Interrupt Service
A subset of the exception vectors are reserved for the control of devices external to, or
embedded in, the processor. These vectors include:
Vector 15 Uninitialized interrupt vector
Vector 24 Spurious interrupt
Vectors 25 Interrupt priority level 1 (lowest)
to
Vector 30 Interrupt priority level 6 (highest)
Vector 31 Interrupt priority level 7 (Non-Maskable)
Vectors 64 User assignable interrupts
to 255
The external interrupt facility is enabled by setting the interrupt mask in the processor
status register (
SR) to 0 thereby enabling interrupts from priority levels 1 to 6. Note that
interrupt priority level 7 cannot be inhibited.
The external interrupt facility is disabled by setting the interrupt mask in the processor
status register (SR) to 6 thereby inhibiting interrupts from priority levels 1 to 6 inclusive.
AMX never sets the processor interrupt mask to 7.
When an interrupt occurs at priority level
n, the processor pushes zero or more words of
processor dependent information on the current stack. The return address (current
Program Counter) and the content of the processor status register are then pushed onto
the current stack. The processor interrupt mask is set to
n thereby disabling all external
interrupts of priority less than or equal to n.
The interrupting device then identifies the interrupt source. In most cases, the device lets
the processor use the interrupt priority level n vector. However, devices can be designed
to present the processor with their own vector number. Any vector number in the range 0
to 255 is possible, but vectors 64 to 255 are reserved for this purpose. Programmable
devices which have not been programmed with their particular vector number usually
respond with vector number 15 signifying an uninitialized interrupt. If no device
responds to the processor's demand for interrupt acknowledgment, the processor uses the
spurious interrupt vector number 24.