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AMX 68000 Target Guide
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3.3 AMX Interrupt Priority and NMI
The M68000 family of processors offers inherent interrupt priority ordering. The AMX
Interrupt Supervisor supports this feature and allows the nesting of interrupts for fast
response to high priority events.
The M68000 interrupt priority mask in the status (SR) register establishes the current
interrupt priority. Tasks run at interrupt priority level 0 with all interrupt sources
enabled. Some interrupts may be specifically disabled by an external interrupt controller.
Tasks must NOT alter the interrupt priority level to any level other than 0 (enabled) or
6 (disabled). Doing so will interfere with the interrupt nesting support provided by
AMX.
Interrupt Service Procedures run at the interrupt priority level dictated by the interrupt
source. An ISP must NOT set the interrupt priority level to any level numerically lower
than the level of the interrupt which it is servicing.
Non-Maskable Interrupt
The Motorola M68000 processor provides a non-maskable priority level 7 interrupt
(NMI). This interrupt cannot be inhibited by software. The processor will respond to
any transition from interrupt request levels 0 to 6 to level 7 by generating a non-maskable
interrupt. When the non-maskable interrupt occurs, the processor automatically saves
zero or more processor dependent parameters, the return address and the processor status
register on the current stack. The processor then vectors to a memory address determined
by the level 7 interrupt autovector (vector number 31) in the Exception Vector Table.
You have complete control over the non-maskable interrupt ISP. Usually, the NMI
interrupt is used to signal a catastrophic event such as a pending loss of power. The NMI
ISP must not use any AMX services. The ISP must process the interrupt in an
application-dependent fashion, restore all registers and return to the point of interruption
if feasible. This ISP must assure that the interrupt facility is restored according to its
state at the time the non-maskable interrupt occurred.
Warning!
Because the occurrence of an NMI interrupt cannot be
controlled, the NMI interrupt can occur at any instant,
including within critical sections of AMX.
Consequently, the NMI ISP cannot use AMX service
procedures for task communication.