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AMX 68000 Target Guide
Vectors in RAM
In most cases, the processor Exception Vector Table will be located in alterable RAM at
address 0 or at some alternate address provided by you. Therefore check this box.
If your processor Exception Vector Table is in ROM, leave this box unchecked. In this
case, you must initialize the ROM vector table for AMX use as directed in Chapter 3.6.
Vectors Not Alterable
Even if the processor Exception Vector Table will be located in RAM, you can still
prevent AMX from altering it. To do so, check this box. In this case, be sure to initialize
the vectors for AMX use as directed in Chapter 3.6.
Vector Table Location
For most M68000 processors, the Exception Vector Table is located in RAM at memory
address 0. However, some processors include a Vector Base Register (VBR) which can
be used to relocate the base of the Exception Vector Table elsewhere in memory.
If you wish AMX to derive the address of the Exception Vector Table, select derived
from the pull down list. If your selected processor has a VBR, AMX will read the VBR
at launch time to derive the address of the Exception Vector Table. If you are using a
processor that does not have a VBR, AMX will assume that the Exception Vector Table
is at address 0 as is appropriate for such processors.
If you wish AMX to set the address of the Exception Vector Table, select adjustable from
the pull down list and enter the base address for the table. Specify the hexadecimal
memory address of the alternate table. If your selected processor has a VBR, AMX will
install the specified base address into the VBR at launch time, thereby establishing that
address as the base address of the Exception Vector Table. If you are using a processor
that does not have a VBR, AMX will ignore the base address parameter and assume that
the Exception Vector Table is at address 0 as is appropriate for such processors.
In some cases, your Exception Vector Table may be in ROM with support for a shadow
vector table in RAM. For example, assume that you use an MC68000 with ROM located
at address 0. The processor does not have a Vector Base Register; it assumes that the
Exception Vector Table is located at address 0. Now, assume that the ROM at address 0
includes a monitor which intercepts all interrupts and exceptions and dispatches each
according to entries in a shadow vector table located at address
$F0000. For such a case,
select shadowed from the pull down list and enter the base address of the shadow vector
table ($F0000 in this example). Specify the hexadecimal memory address of the shadow
vector table. AMX will ignore the VBR, if one exists, and assume that the processor
Exception Vector Table is at the specified base address.