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AMX 68000 Target Guide
Vector Base Register
The VBR parameter is used to specify the memory address at which the Exception Vector
Table is located. For most applications, the Exception Vector Table is located at address
0. You can use the
VBR parameter to redefine the location of the Exception Vector Table
or to define its location in ROM.
At launch, AMX installs the address specified by parameter VBR into the processor's
Vector Base Register (VBR), if one exists for the processor specified by parameter
PROC.
If parameter VBR is set to -1, AMX will leave the VBR unaltered and will read its content
at launch time to determine the address of the Exception Vector Table.
If you are using a processor that does not have a VBR, set parameter VBR to 0. AMX will
assume that the Exception Vector Table is at address 0 as is appropriate for such
processors.
Shadow Vector Table Location
In some cases, your Exception Vector Table may be in ROM with support for a shadow
vector table in RAM. For example, assume that you use an MC68000 with ROM located
at address 0. The processor does not have a Vector Base Register; it assumes that the
Exception Vector Table is located at address 0. Now, assume that the ROM at address 0
includes a monitor which intercepts all interrupts and exceptions and dispatches each
according to entries in a shadow vector table located at address $F0000.
To use AMX in this example, the ...HDW parameter VBR must be set to 0 and the
following directive must be present in the Target Parameter File.
...VBASE $F0000
AMX will assume that the Exception Vector Table is at address $F0000. If the processor
has a Vector Base Register, AMX will ignore its content and leave it unaltered.