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To detect bus contention
In this sequencer setup, the trigger occurs only if both devices assert their
bus transfer acknowledge lines at the same time.
1
Select the timing analyzer Trigger menu.
2 Define the Edge1 term to represent assertion of the bus transfer
acknowledge line of one device, and Edge2 term to represent
assertion of the bus transfer acknowledge line of the other device.
You can rename these to BTACK1 and BTACK2.
3 Under Timing Sequence Levels, enter the following sequence
specification:
TRIGGER on “BTACK1 • BTACK2” 1 time
Triggering on Bus Contention
Triggering
To detect bus contention
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