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Hardware options installation 43
• If there is one quad-rank LVDIMM per channel on any populated memory channel in the system running
at 1066 MHz, the LVDIMMs operate at 1.5V.
This setting preserves maximum memory subsystem performance. To have DIMMs operate at 1.35V,
configure the Maximum Memory Bus Frequency option in the ROM-Based Setup Utility to 800 MHz.
LVDIMMs are only supported for use with the Intel® Xeon® 5600 series of processors.
Advanced ECC memory configuration
Advanced ECC memory is the default memory protection mode for this server. Standard ECC can correct
single-bit memory errors and detect multi-bit memory errors. When multi-bit errors are detected using
Standard ECC, the error is signaled to the server and causes the server to halt.
Advanced ECC protects the server against some multi-bit memory errors. Advanced ECC can correct both
single-bit memory errors and 4-bit memory errors if all failed bits are on the same DRAM device on the DIMM.
Advanced ECC provides additional protection over Standard ECC because it is possible to correct certain
memory errors that would otherwise be uncorrected and result in a server failure. The server provides
notification that correctable error events have exceeded a pre-defined threshold rate.
Mirrored memory configuration
Mirroring provides protection against uncorrected memory errors that would otherwise result in server
downtime. Mirroring is performed at the channel level. Channels 1 and 2 are used; channel 3 is not
populated.
Data is written to both memory channels. Data is read from one of the two memory channels. If an
uncorrectable error is detected in the active memory channel, data is retrieved from the mirror channel. This
channel becomes the new active channel, and the system disables the channel with the failed DIMM.
Online Spare memory configuration
Online spare memory provides protection against degraded DIMMs by reducing the likelihood of
uncorrected memory errors. This protection is available without any operating system support.
Online spare memory protection dedicates one rank of each memory channel for use as spare memory. The
remaining ranks are available for OS and application use. If correctable memory errors occur at a rate
higher than a specific threshold on any of the non-spare ranks, the server automatically copies the memory
contents of the degraded rank to the online spare rank. The server then deactivates the failing rank and
automatically switches over to the online spare rank.
Lockstep memory configuration
Lockstep mode provides protection against multi-bit memory errors that occur on the same DRAM device.
Lockstep mode can correct any single DRAM device failure on x4 and x8 DIMM types. The DIMMs in each
channel must have identical HP part numbers.
Lockstep mode uses channel 1 and channel 2. Channel 3 is not populated. Because channel 3 cannot be
populated when using Lockstep mode, the maximum memory capacity is lower than Advanced ECC mode.
Memory performance with Advanced ECC is also slightly higher.
General DIMM slot population guidelines
Observe the following guidelines for all AMP modes: