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Chapter 2. IBM Eserver BladeCenter overview 11
The BladeCenter HS20 uses the Intel® Lindenhurst chipset (see the HS20 architecture in
Figure 2-6).
Figure 2-6 HS20 architecture
The Intel Lindenhurst chipset consists of the following components:
Memory and I/O controller (MCH) (North Bridge)
PXH-D
ICH-S (South Bridge)
The Lindenhurst MCH, Memory and I/O controller provides the interface between the
processors, the memory, and the PCI Express busses that interface to the other Intel chips.
The Lindenhurst ICH-S (South Bridge) provides the USB interfaces, the local Service
Processor interface, the POST/BIOS flash EEPROM interface, and the PCI bus interface for
the ATI Radeon Mobility Video controller and LSI 1020 SCSI Host Controller. The PXH
interfaces the Broadcom BCM5704S ethernet controller on its secondary bus and the
daughter card on its secondary bus. I/O functions on the 8843 include Video, I2C, USB,
SCSI, Gigabit Ethernet, and USB (floppy, CD-ROM (DVD), mouse, and keyboard).
The LPC bus is used to connect to the POST/BIOS EEPROM on the 8843. The size of the
EEPROM is 4 MB x 8, and it contains primary BIOS, backup BIOS, and blade diagnostics.
VRM 10.1
Nocona
XEON
CPU
Nocona
XEON
CPU
VRM 10.1
MCH
ICH-S
PCI
bus 0
VPD 32KB
EEPROM
LSI
1020
SCSI
ATI
7000M
SCSI HDD Connector 1
SCSI HDD Connector 1
Blade
Expansion
Connector
Renassas
SP (2166)
Broadcom
5704S Ethernet
controller
PXH
Pri Sec
Daughter card connector
Blade HD
connector A
Midplane HD
connector A
Blade HD
connector B
Midplane HD
connector B
8843 HS20 Block Diagram
Due to space
limitations this
diagram is not
drawn to scale
Servicing the IBM ^
HS20 (M/T 8843) and Blade
Storage Expansion-II Option
To SP I
2
C bus
Hublink 1.5
Data A
Data B
I
2
C bus
LPC
PCI
32/33
PCI Express x4
PCIX C
Video
PCIX B
PCIX 66
1Gb Ethernet
1 Gb
Ethernet
Video
To SP I
2
C bus
PCIExpress x8
DDR2
400Mhz 2GB
DIMMs
sockets
USB ports to
HD connectors
To SP
I
2
C bus