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©2004 Inova Computers GmbH Page 2-11Doc. PD00941013.001
ICP-CM
Configuration
CompactPCI
®
2
2.8 Timer / Counter
The IBM-compatible architecture configures the programmable timer / counter (Intel 8254-com-
patible) devices for system-specific functions as shown in Table 2.80.
The BIOS programs Timer 0 to generate an interrupt approximately every 55ms (18.2 times per
second.) This interrupt, known as the system timer tick, updates the BIOS clock and turns off the
floppy disk motor drive after a few seconds of inactivity for example.
The BIOS featured in Inova’s CPUs programs the system timer tick for PC compatibility. The inter-
rupt generated by the timer creates an interrupt request on IRQ0 of the programmable interrupt
controller (PIC) which is serviced by the CPU as interrupt vector 08h.
In addition, Timer 1 and Timer 2 are also initialised by the BIOS as necessary for the specific
‘processor board functions.
Table 2.80 Timer and Counter Functions
Timer Function/Assignment
Timer 0 System Timer, Periodic Interrupt (55 ms)
Timer 1 SDRAM Refresh
Timer 2 Speaker Frequency Generator
2.9 Watchdog
Two independent watchdog timers are implemented in the ICP-CM. The first timer, residing in the
SiS962 South-Bridge, has a range from 4ms to 255 hours and can issue either a Reset or SMI
(System Management Interrupt) upon expiry. The second timer in the Super I/O controller ranges
from 1 minute to 255 minutes and issues either a Reset, IRQ or SMI upon timeout.
Note:
An OS-specific driver is required to
configure the watchdog timer. Please
refer to the Inova WWW support
pages (http://www.inova-
computers.de/web/support/public/
index.html) for the latest versions or
contact Inova hotline support directly
for advice .