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Intel® 41110 Serial to Parallel PCI Bridge Design Guide 29
PCI-X Layout Guidelines 8
This chapter describes several factors to be considered with a 41110 PCI/PCI-X design. These
include the PCI IDSEL, PCI RCOMP, PCI Interrupts and PCI arbitration.
8.1 Interrupts
PCI Express provides interrupt messages that emulate the legacy wired mechanism. This allows IO
devices to signal PCI-style interrupts using a pair of ASSERT and DEASSERT messages This
message pairing preserves the level-sensitive semantics of the PCI interrupts on PCI Express.
The 41110 uses four interrupts - A_INTA:A_INTD on bus A segment corresponding to the four
interrupts defined in the PCI specification. The 41110 routes its PCI interrupt pins and the internal
interrupts to PCI Express INTx interrupts according to Table 4.
Table 4. INTx Routing Table
The 41110 will use its primary bus number and device number in the Requester ID field for the PCI
Express INTx messages. As stated in the PCI Express specification, the function number is
reserved for interrupt messages and will always be 0.
A_INT# Interrupt Pins PCI Express INTx Message
A_INTA INTA
A_INTB INTB
A_INTC INTC
A_INTD INTD