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Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families 147
Datasheet Volume One
Signal Descriptions
6.5 PECI Signal
6.6 System Reference Clock Signals
6.7 JTAG and TAP Signals
Note: Refer to the appropriate Platform Design Guide (PDG) for Debug Port implementation details.
Table 6-10. PECI Signals
Signal Name Description
PECI PECI (Platform Environment Control Interface) is the serial sideband interface to the
processor and is used primarily for thermal, power and error management. Details
regarding the PECI electrical specifications, protocols and functions can be found in the
Platform Environment Control Interface Specification.
Table 6-11. System Reference Clock (BCLK{0/1}) Signals
Signal Name Description
BCLK{0/1}_D[N/P] Reference Clock Differential input. These pins provide the PLL reference clock
differential input into the processor. Both 100MHz BCLK0 and BCLK1 from the same
clock source provide the required reference clock inputs to the various PLLs inside
the CPU.
Table 6-12. JTAG and TAP Signals
Signal Name Description
BPM_N[7:0]
Breakpoint and Performance Monitor Signals: I/O signals from the processor that
indicate the status of breakpoints and programmable counters used for monitoring
processor performance. These are 100 MHz signals.
EAR_N
External Alignment of Reset, used to bring the processor up into a deterministic state.
This signal is pulled up on the die, refer to Table 7-6 for details.
PRDY_N
Probe Mode Ready is a processor output used by debug tools to determine processor
debug readiness.
PREQ_N
Probe Mode Request is used by debug tools to request debug operation of the
processor.
TCK
TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the
Test Access Port).
TDI
TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial
input needed for JTAG specification support.
TDO
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the
serial output needed for JTAG specification support.
TMS TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
TRST_N
TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must be driven
low during power on Reset.