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60 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
2.5.2.7 RdIAMSR()
The RdIAMSR() PECI command provides read access to Model Specific Registers
(MSRs) defined in the processor’s Intel® Architecture (IA). MSR definitions may be
found in the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM)
Volumes 1, 2, and 3. Refer to Table 2-11 for the exact listing of processor registers
accessible through this command.
2.5.2.7.1 Command Format
The RdIAMSR() format is as follows:
Write Length: 0x05
Read Length: 0x09 (qword)
Command: 0xb1
Description: Returns the data maintained in the processor IA MSR space as specified
by the ‘Processor ID’ and ‘MSR Address’ fields. The Read Length dictates the desired
data return size. This command supports only qword responses. All command
responses are prepended with a completion code that contains additional pass/fail
status information. Refer to Section 2.5.5.2 for details regarding completion codes.
2.5.2.7.2 Processor ID Enumeration
The ‘Processor ID’ field that is used to address the IA MSR space refers to a specific
logical processor within the CPU. The ‘Processor ID’ always refers to the same physical
location in the processor silicon regardless of configuration as shown in the example in
Figure 2-42. For example, if certain logical processors are disabled by BIOS, the
Processor ID mapping will not change. The total number of Processor IDs on a CPU is
product-specific.
‘Processor ID’ enumeration involves discovering the logical processors enabled within
the CPU package. This can be accomplished by reading the ‘Max Thread ID’ value
through the RdPkgConfig() command (Index 0, Parameter 3) described in
Section 2.5.2.6.12 and subsequently querying each of the supported processor
threads. Unavailable processor threads will return a completion code of 0x90.
Alternatively, this information may be obtained from the RESOLVED_CORES_MASK
register readable through the RdPCIConfigLocal() PECI command described in
Section 2.5.2.9 or other means. Bits [7:0] and [9:8] of this register contain the ‘Core
Mask’ and ‘Thread Mask’ information respectively. The ‘Thread Mask’ applies to all the
enabled cores within the processor package as indicated by the ‘Core Mask’. For
the processor PECI clients, the ‘Processor ID’ may take on values in the range 0
through 15.