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12 Intel Server Board SE7500CW2 Product Guide
Intel
®
E7500 Chipset
The Server Board SE7500CW2 includes an Intel
E7500 chipset (MCH, ICH3, P64H2) that provides
an integrated I/O bridge and memory controller and a flexible I/O subsystem core (PCI).
MCH
The MCH North Bridge in the E7500 chipset integrates three main functions:
• An integrated high-performance main memory subsystem
• An HI 2.0 bus interface that provides a high-performance data flow path between the host bus
and the I/O subsystem
• A HI 1.5 bus that provides an interface to the ICH3-S (South Bridge)
Other features provided by the MCH include the following:
• Full support of ECC on the memory bus
• Full support of chipkill on the memory interface with x4 DIMMs
• Twelve deep in-order queue
• Full support of registered DDR-200 or DDR-266 ECC DIMMs
• Memory scrubbing
ICH3
The primary role of the ICH3 is to provide the gateway to all PC-compatible I/O devices and
features. The Server Board SE7500CW2 uses the following ICH3 features:
• 32-bit/33 MHz PCI bus interface
• LPC bus interface
• IDE interface, with Ultra DMA 100 capability
• USB interface
• PC-compatible timer/counter and DMA controllers
• APIC and 8259 interrupt controller
• Power management
• System real-time clock (RTC)
• General purpose I/O