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KS152JB Universal Communications Controller
Technical Specifications
Kawasaki LSI USA, Inc. Page 17 of 120 Ver. 0.9 KS152JB2
Interrupt enable register for DMA and GSC interrupts. A 1 in any bit position enables that interrupt.
IEN1.0 (EGSRV) - Enables the GSC valid receive interrupt.
IEN1.1 (EGSRE) - Enables the GSC receive error interrupt.
IEN1.2 (EDMA0) - Enables the DMA done interrupt for channel 0.
IEN1.3 (EGSTV) - Enables the GSC valid transmit interrupt.
IEN1.4 (EDMA1) - Enables the DMA done interrupt for Channel1.
IEN1.5 (EGSTE) - Enables the GSC transmit error interrupt.
Allows the user software two levels of prioritization to be assigned to each of the interrupts in
IEN1. A 1 assigns the corresponding interrupt in IEN1 a higher interrupt than an interrupt with a
corresponding 0.
IPN1.0 (PGSRV) - Assigns the priority of GSC receive valid interrupt.
IPN1.1 (PGSRE) - Assigns the priority of GSC error receive interrupt.
IPN1.2 (PDMA0) - Assigns the priority of DMA done interrupt for Channel 0.
IPN1.3 (PGSTV) - Assigns the priority of GSC transmit valid interrupt.
IPN1.4 (PDMA1) - Assigns the priority of DMA done interrupt for Channel 1.
IPN1.5 (PGSTE) - Assigns the priority of GSC transmit error interrupt.
01234567
EDMA1 EGSTV EDMA0 EGSRE EGSRVEGSTE
IEN1 (Additional interrupt enable register) (0C8H)
01234567
PDMA1 PGSTV PDMA0 PGSRE PGSRVPGSTE
IPN1 (Additional interrupt priority register) (0F8H)