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KS152JB Universal Communications Controller
Technical Specifications
Kawasaki LSI USA, Inc. Page 65 of 120 Ver. 0.9 KS152JB2
to each station. When using 16-bit addressing, ADR0:ADR1 form one address and ADR2:ADR3
form the second address. If the receiver is enabled, it looks for a matching address after every
BOF flag is detected. As the data is received, if the 8th (or 16th) bit does not match the address
recognition circuitry, the rest of the frame is ignored and the search continues for another flag. if
the address does match the address recognition circuitry, the address and all subsequent data is
passed into the receive FIFO until the EOF flag or an error occurs. The address is not stripped and
is also passed to RFIFO.
The address masking registers, AMSK0 and AMSK1, work in conjunction with ADR0 and ADR1
respectively to identify “don’t care” bits. A 1 in any position in the AMSKn register makes the
respective bit in the ADRn register irrelevant. These combinations can then be used for form
group addresses. If the masking registers are filled with all 1s, the C152 will receive all packets,
which is called the promiscuous mode. If 16-bit addressing is used, AMSK0:AMSK1 form one
16-bit address mask.
3.6 GSC Operation
3.6.1 Determining Line Discipline
In normal operation the GSC uses full or half duplex operation. When using a 32-bit CRC
(GMOD.3 = 1), operation can only be half duplex. If using a 16-bit CRC (GMOD.3 = 0), full
duplex is selected by default. When using a 16-bit CRC the receiver can be turned off while trans-
mitting (RSTAT.1 = 0), and the transmitter can be turned off during reception (TSTAT.1 = 0). This
simulates half-duplex operation when using a 16-bit CRC.
Normally, HDLC uses a 16-bit CRC, so half duplex is determined by turning off the receiver or
transmitter. This is so that the receiver will not detect its own address as transmission takes place.
This also needs to be done when using CSMA/CD with a 16-bit CRC for the same reason.
3.6.2 CPU/DMA CONTROL OF THE GSC
The data for transmission or reception can be handled by either the CPU (TSTAT.0 = 0) or DMA
controller (TSTAT.0 = 1). This allows the user two sets of flags to control the FIFO. Associated
with these flags are interrupts, which may be enabled by the user software. Either one or both sets
of flags may be used at the same time.
In CPU control mode the flags (RFNE, TFNF) are generated by the condition of the receive or
transmit FIFO’s. After loading a byte into the transmit FIFO, there is a one machine cycle latency
until the TFNF flag is updated. Because of this latency, the status of TFNF should not be checked
immediately following the instruction to load the transmit FIFO. If using the interrupts to service
the transmit FIFO, the one machine cycle of latency must be considered if the TFNF flag is
checked prior to leaving the subroutine.
When using the CPU for control, transmission normally is initiated by setting TEN bit (TSTAT.1)