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KS152JB Universal Communications Controller
Technical Specifications
Kawasaki LSI USA, Inc. Page 97 of 120 Ver. 0.9 KS152JB2
The UR bit can be set only if the DMA bit in the TSTAT is set. The DMA bit being set informs the
GSC hardware that TFIFO is being serviced by DMA. In that case if the GSC goes to fetch
another byte from TFIFO and finds it empty, and the byte count register of the DMA channel ser-
vicing TFIFO is not zero, it sets the UR bit.
If the DMA hardware is not being used to service TFIFO, the UR bit cannot get set. If the DMA
bit is 0, then when the GSC finds TFIFO empty, it assumes that the transmission of data is com-
plete and the transmission of CRC bits can begin.
The NOACK bit is functional only in CSMA/CD mode, and only when the HABEN bit in RSTAT
is set. The HABEN bit turns on the Hardware Based Acknowledge feature, as described in Sec-
tion 3.2.6. If this feature is not invoked, the NOACK bit will stay at 0.
If the NOACK bit gets set, it means the GSC has completed a transmission, and was expecting to
receive a hardware based acknowledge from the receiver of the message, but did not receive the
acknowledge, or at least did not receive it cleanly. There are three ways the NOACK can get set:
1. The acknowledge signal (an unattached preamble) was not received before the IFS was com-
plete.
2. A collision was detected during the IFS
3. The line was active during the last bit-time of the IFS
The first condition is an obvious reason for setting the NOACK bit, since that’s what the hardware
based acknowledge is for. The other two ways the NOACK bit can get set are to guard against the
possibility that the transmitting station might mistake an unrelated transmission or transmission
fragment for an acknowledge signal.
5.2 GSC Receiver Error Conditions
The GSC Receiver section reports four kinds of error conditions:
CRCE - CRC error
AE - Alignment Error
RCABT - Receive Abort
OVR - Overrun in Receive FIFO
These bits reside in the RSTAT register. User software can read them, but only GSC hardware can
write to them. The GSC hardware will set them in response to the various error conditions that
they represent. When user software sets the GREN bit, the GSC hardware will at that time clears
these flags. This is the only way these flags can be cleared.
The logical OR of these four bits flags the GSC Receive Error interrupt (GSCRE) and clears the
GREN bit, as shown in Figure below. Note in this figure that any error condition will prevent