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Manual for PlatiniX 2 series
Chapter 3
Advanced Chipset Features Setup
Figure-5 Advanced Chipset Features Menu
The following indicates the options for each item and describes their meaning.
Item Option Description
#"DRAM Timing
By User
DRAM timing is defined by user.
Selectable
By SPD
DRAM timing is defined by SPD.
#"CAS Latency
1.5~3
Set CAS latency time.
Time
#"Active to Precharge
5,6,7
Set precharge delay time.
Delay
#"DRAM RAS# to
2,3
Set DRAM RAS# to CAS# delay 3 SCLKs or 2
CAS# Delay SCLKs.
#"DRAM RAS#
2,3
Set DRAM RAS# precharge as 3 or 2.
Precharge
#"DRAM Data
ECC
This option allows you to select the Parity or ECC
Integrity Mode
Non-ECC
(Error-Checking and Correcting), according to the
type of installed DRAM.
#"System BIOS
Enabled
Besides conventional memory, the system BIOS
Cacheable area is also cacheable.
Disabled
System BIOS area is not cacheable.
#"Video BIOS
Enabled
Besides conventional memory, video BIOS area
Cacheable is also cacheable.
Disabled
Video BIOS area is not cacheable.