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(3) Multiplex Bus Timing
Table 5.4 and Figure 5.3 show the bus timing in memory expansion and microprocessor modes (with
wait, accessing external area, using multiplex bus).
Table 5.4 Memory expansion and microprocessor modes (with wait, accessing external area, using multiplex bus)
*1 Calculated by the following formula accord-
ing to the frequency of BCLK.
th(RD-AD)=
+0 [ns]
10
9
f(BCLK)x2
th(WR-AD)=
+0 [ns]
10
9
f(BCLK)x2
th(RD-CS)=
+0 [ns]
10
9
f(BCLK)x2
th(WR-CS)=
+0 [ns]
10
9
f(BCLK)x2
th(DB-WR)=
-50 [ns]
10
9
x3
f(BCLK)x2
th(WR-DB)=
+0 [ns]
10
9
f(BCLK)x2
th(AD-ALE)=
-40 [ns]
10
9
f(BCLK)x2
*2 Calculated by the following formula accord-
ing to the frequency of BCLK.
th(WR-AD)=
-6 [ns]
10
9
f(BCLK)x2
th(WR-CS)=
-6 [ns]
10
9
f(BCLK)x2
th(WR-DB)=
-12 [ns]
10
9
f(BCLK)x2
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
td(AD-WR)
tdz(RD-AD)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip-select output delay time
Chip-select output hold time (BCLK standard)
Chip-select output hold time (RD standard)
Chip-select output hold time (WR standard)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)
ALE output delay time (BCLK standard)
ALE output hold time (BCLK standard)
ALE output delay time (Address standard)
ALE output hold time (Address standard)
After address RD signal output delay time
After address WR signal output delay time
Address output floating start time
Symbol
Item
Actual MCU
[ns]
This product
[ns]
Min.
Min.
Max.
4
(*1)
(*1)
4
(*1)
(*1)
0
0
4
(*1)
(*1)
-4
(*1)
30
0
0
50
50
40
40
50
40
8
See left
See left
(*2)
See left
(*2)
(*2)
See left
See left
See left
(*2)
(*2)
See left
See left
See left
-4
-3
Max.
See left
See left
See left
See left
See left
See left
17