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Si5351A/B/C
Preliminary Rev. 0.95 37
Reset value = 0000 0000
Register 23. CLK7 Control
BitD7D6D5D4D3D2D1D0
Name
CLK7_PDN FBB_INT MS7_SRC CLK7_INV CLK7_SRC[1:0] CLK7_IDRV[1:0]
Type
R/W R/W R/W R/W R/W R/W
Bit Name Function
7 CLK7_PDN Clock 7 Power Down.
This bit allows powering down the CLK7 output driver to conserve power when the out-
put is unused.
0: CLK7 is powered up.
1: CLK7 is powered down.
6 FBB_INT FBB MultiSynth Integer Mode.
Set this bit according to ClockBuilder Desktop generated register map file.
5MS7_SRCMultiSynth Source Select for CLK7.
0: Select PLLA as the source for MultiSynth0.
1: Select PLLB (Si5351A/C only) or VCXO (Si5351B only) MultiSynth0.
4 CLK7_INV Output Clock 7 Invert.
0: Output Clock 7 is not inverted.
1: Output Clock 7 is inverted.
3:2 CLK7_SRC[1:0] Output Clock 0 Input Source.
These bits determine the input source for CLK7.
00: Select the XTAL as the clock source for CLK7. This option by-passes both synthe-
sis stages (PLL/VCXO & MultiSynth) and connects CLK7 directly to the oscillator
which generates an output frequency determined by the XTAL frequency.
01: Select CLKIN as the clock source for CLK7. This by-passes both synthesis stages
(PLL/VCXO & MultiSynth) and connects CLK7 directly to the CLKIN input. This essen-
tially creates a buffered output of the CLKIN input.
10: Reserved. Do not select this option.
11: Select MultiSynth 0 as the source for CLK7. Select this option when using the
Si5351 to generate free-running or synchronous clocks.
1:0 CLK7_IDRV[1:0] CLK7 Output Rise and Fall time / Drive Strength Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA