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Chapter 1: Introduction
1-9
Introduction
1-2 Chipset Overview
Built upon the functionality and capabilities of the E7525 chipset, the X6DAT-
G/X6DAi-G motherboard provides the performance and feature set required
for dual processor-based computer systems, with configuration options
optimized for communications, presentation, storage, computation and data-
base applications. The Intel E7525 chipset consists of the following compo-
nents: the Memory Controller Hub (MCH), and the I/O Controller Hub (6300
ESB ICH).
MCH
The MCH supports single or dual Xeon EM64T processors with a Front Side
Bus speed of 800 MHz*. Its memory controller provides direct connection to
two channels of registered DDR333 with a marched system bus address
and data bandwidths of up to 2.67 GB/s (DDR333) per channel. The MCH
also supports the new PCI Express high speed serial I/O interface for supe-
rior I/O bandwidth and provides configurable x16 and x8 PCI Express inter-
faces. These interfaces support connection of the MCH to a variety of other
bridges that are compliant with the PCI Express Interface Specification Rev.
1.0a. The MCH interfaces with the 6300ESB ICH I/O Controller Hub via HI
1.5 Hub Interface to support 32-bit or 64-bit PCI devices running at 33 or 66
MHz.
6300 ESB (Hance Rapids) ICH System Features
In addition to providing the I/O subsystem with access to the rest of the
system, the Hance Rapids ICH I/O Controller Hub integrates many I/O
functions.
The 6300 ESB Hance Rapids ICH I/O Controller Hub integrates: 2-channel
Ultra ATA/100 Bus Master IDE Controller, two Serial ATA (SATA) Host Con-
trollers, SMBus 2.0 Controller, LPC/Flash BIOS Interface, PCI-X (66MHz) In-
terface, PCI 2.2 Interface and System Management Controller.
*Note: The CPU FSB speed is set at 800 MHz by the Manufacturer.
Please do not change the this setting.