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X7DBT/X7DBT-INF/X7DGT/X7DGT-INF User's Manual
B. The Intel 5000X Chipset (*for the X7DGT/X7DGT-INF)
Built upon the functionality and the capability of the 5000X (Greencreek) chipset,
the X7DGT/X7DGT-INF motherboard provides the performance and feature set
required for dual processor-based servers with confi guration options optimized
for communications, presentation, storage, computation or database applications.
The 5000X chipset supports single or dual Xeon 64-bit dual core processor with
front side bus speeds of up to 1333 MHz. The chipset consists of the 5000X
Memory Controller Hub (MCH) and the Enterprise South Bridge 2 (ESB2).
The 5000X MCH chipset is designed for symmetric multiprocessing across two
independent front side bus interfaces. Each front side bus uses a 64-bit wide,
1333 MHz data bus that transfers data at 10.7 GB/sec. The MCH chipset connects
up to 8 Fully Buffered DIMM modules, providing a total of 32.0 GB/s for DDR2
667/533 memory. The MCH chipset also provides one x8 PCI-Express and one
x4 ESI interface to the ESB2. In addition, the 5000X chipset offers a wide range
of RAS features, including memory interface ECC, x4/x8 Single Device Data
Correction, CRC, parity protection, memory mirroring and memory sparing.
Xeon Dual Core Processor Features
Designed to be used with conjunction of the 5000X chipset, the Xeon Dual Core
Processors provide a feature set as follows:
The Xeon Dual Core Processors
*L1 Cache Size: Instruction Cache (32KB/16KB), Data Cache (32KB/24KB)
*L2 Cache Size: 4MB/2MB (per core)
*Data Bus Transfer Rate: 8.5 GB/s
*Package: FC-LGA6/FC-LGA4, 771 Lands