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TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
receive filtering of frames
Received frames that contain an error (e.g., CRC, alignment, jabber, etc.) are discarded before transmission
and the relevant statistics counter is updated.
data transmission
The MAC takes data from the TNETX3270 internal buffer memory and passes it to the PHY. The data also is
synchronized to the transmit clock rate.
A CRC block verifies that the outgoing frame has not been corrupted within the switch by verifying that it still
has a valid CRC as the frame is being transmitted. If a CRC error is detected, it is counted in the transmit data
errors counter.
transmit control
The frame control block handles the output of data to the PHYs. Several error states are handled. If a collision
is detected, the state machine jams the output. If the collision was late (after the first 64-byte buffer has been
transmitted), the frame is lost. If it is an early collision, the controller backs off before retrying. While operating
in full duplex, both carrier-sense (CRS) mode and collision-sensing modes are disabled (the switch does not
start transmitting a new frame if collision is active in full-duplex mode).
Internally, frame data only is removed from buffer memory once it has been successfully transmitted without
collision (for the half-duplex ports). Transmission recovery also is handled in this state machine. If a collision
is detected, frame recovery and retransmission are initiated.
adaptive performance optimization (APO) (transmit pacing)
Each Ethernet MAC incorporates APO logic. This can be enabled on an individual port basis. When enabled,
the MAC uses transmission pacing to enhance performance (when connected on networks using other transmit
pacing-capable MACs). Adaptive performance pacing introduces delays into the normal transmission of
frames, delaying transmission attempts between stations, reducing the probability of collisions occurring during
heavy traffic (as indicated by frame deferrals and collisions), thereby, increasing the chance of successful
transmission.
When a frame is deferred, suffers a single collision, multiple collisions, or excessive collisions, the pacing
counter is loaded with an initial value of 31. When a frame is transmitted successfully (without a deferral, single
collision, multiple collision, or excessive collision), the pacing counter is decremented by 1, down to 0.
With pacing enabled, a new frame is permitted to immediately [after one inter-packet gap (IPG)] attempt
transmission only if the pacing counter is 0. If the pacing counter is not 0, the frame is delayed by the pacing
delay (a delay of approximately four interframe gap delays).
NOTE:
APO affects only the IPG preceding the first attempt at transmitting a frame. It does not affect the
backoff algorithm for retransmitted frames. APO should be used only with other endstations that
also support APO.
interframe gap enforcement
The measurement reference for the interpacket gap of 96-bit times is changed, depending on frame traffic
conditions. If a frame is transmitted successfully (without collision), 96-bit times is measured from MxxTXEN.
If the frame suffered a collision, 96-bit times is measured from MxxCRS.
backoff
The device implements the IEEE Std 802.3 binary exponential backoff algorithm.