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TNETX3270
ThunderSWITCH 24/3 ETHERNET SWITCH
WITH 24 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS
SPWS043B – NOVEMBER 1997 – REVISED APRIL 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
10-/100-Mbit/s MAC interface (ports 24–26) (continued)
†
TERMINAL
I/O
INTERNAL
DESCRIPTION
NAME NO.
I/O
RESISTOR
DESCRIPTION
M24RXD3
M24RXD2
M24RXD1
M24RXD0
M25RXD3
M25RXD2
M25RXD1
M25RXD0
M26RXD3
M26RXD2
M26RXD1
M26RXD0
49
48
47
46
73
71
70
69
98
97
96
95
I Pullup
Receive data (nibble receive data from the attached PHY or PMI device). Data on these
signals is synchronous to MxxRCLK. MxxRXD0 is the least significant bit and MxxRXD3
is the most significant bit.
M24RXDV
M25RXDV
M26RXDV
50
75
99
I Pulldown
Receive data valid. When high, MxxRXDV indicates valid data is present on the
MxxRXD3–MxxRXD0 lines.
M24RXER
M25RXER
M26RXER
51
76
101
I Pulldown Receive error. MxxRXER indicates a coding error on received data.
M24TCLK
M25TCLK
M26TCLK
33
56
82
I Pullup Transmit clock. Transmit clock source from the attached PHY or PMI device.
M24TXD3
M24TXD2
M24TXD1
M24TXD0
M25TXD3
M25TXD2
M25TXD1
M25TXD0
M26TXD3
M26TXD2
M26TXD1
M26TXD0
38
37
36
35
61
60
59
57
86
85
84
83
O None
Transmit data (nibble transmit data). When MxxTXEN is asserted, these signals carry
transmit data. Data on these signals is synchronous to MxxTCLK. MxxTXD0 is the least
significant bit and MxxTXD3 is the most significant bit.
M24TXEN
M25TXEN
M26TXEN
39
62
87
O None Transmit enable. MxxTXEN indicates valid transmit data on MxxTXD3–MxxTXD0.
M24TXER
M25TXER
M26TXER
41
63
89
O None
Transmit error. MxxTXER allows coding errors to be propagated across the MII. MxxTXER
is taken high when an under-run in the transmit FIFO for port xx occurs and causes fill data
to be transmitted (MxxTXER is low otherwise). MxxTXER is asserted at the end of an
under-running frame, enabling the device to force a coding error.
†
xx = ports 24, 25, and 26