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Dell Converged Enhanced Ethernet Administrator’s Guide 105
53-1002116-01
Scheduling
10
Figure 8 describes the frame scheduling order for a WRR scheduler servicing two WRR queues. The
higher numbered queue is considered higher priority (WRR2) and the weights indicate the network
bandwidth should be allocated in a 2:1 ratio between the two queues. In Figure 8 WRR2 should
receive 66 percent of bandwidth and WRR1 receives 33 percent. The WRR scheduler tracks the
extra bandwidth used and subtracts it from the bandwidth allocation for the next cycle through the
queues. In this way, the bandwidth utilization statistically matches the queue weights over longer
time periods.
FIGURE 8 WRR schedule — two queues
Deficit Weighted Round Robin (DWRR) is an improved version of WRR. DWRR remembers the
excess used when a queue goes over its bandwidth allocation and reduces the queue's bandwidth
allocation in the subsequent rounds. This way the actual bandwidth usage is closer to the defined
level when compared to WRR.
Traffic class scheduling policy
The traffic classes are numbered from 0 to 7; higher numbered traffic classes are considered
higher priority. The Dell M8428-k provides full flexibility in controlling the number of SP-to-WRR
queues. The number of SP queues is specified in N (SP1 through 8), then the highest priority traffic
classes are configured for SP service and the remaining eight are WRR serviced. Table 20
describes the set of scheduling configurations supported.
When you configure the QoS queue to use strict priority 4 (SP4), then traffic class 7 will use SP4,
traffic class 6 will use SP3, and so on down the list. You use the strict priority mappings to control
how the different traffic classes will be routed in the queue.
TABLE 20 Supported scheduling configurations
Traffic Class SP0 SP1 SP2 SP3 SP4 SP5 SP6 SP8
7 WRR8 SP1 SP2 SP3 SP4 SP5 SP6 SP8
6 WRR7 WRR7 SP1 SP2 SP3 SP4 SP5 SP7
5 WRR6 WRR6 WRR6 SP1 SP2 SP3 SP4 SP6
4 WRR5 WRR5 WRR5 WRR5 SP1 SP2 SP3 SP5
3 WRR4 WRR4 WRR4 WRR4 WRR4 SP1 SP2 SP4
2 WRR3 WRR3 WRR3 WRR3 WRR3 WRR3 SP1 SP3
1 WRR2 WRR2 WRR2 WRR2 WRR2 WRR2 WRR2 SP2
0 WRR1 WRR1 WRR1 WRR1 WRR1 WRR1 WRR1 SP1