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6-10 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE
Table 6-11 describes IVEC Þelds.
6.2.11 RxBD Active Register (R_DES_ACTIVE)
The RxBD active register (R_DES_ACTIVE), shown in Figure 6-11, is a command register
that should be written by the user to indicate that the RxBD ring was updated (empty
receive buffers have been produced by the software driver with the E bit set).
Whenever the register is written, the R_DES_ACTIVE bit is set, regardless of the data
written by the user. While the bit is set, the RxBD ring is polled and receive frames
(provided ECNTRL[ETHER_EN] is also set) are processed. Once an RxBD whose
ownership bit is not set is polled, the R_DES_ACTIVE bit is cleared and polling stops until
the user sets the bit again, signifying additional BDs have been placed into the RxBD ring.
R_DES_ACTIVE is cleared at reset and by clearing ECNTRL[ETHER_EN].
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field ILEVEL Ñ
Reset 0000_0000_0000_0000
R/W Read/write
Addr 0xE4C
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field Ñ IVEC Ñ
Reset 0000_0000_0000_0000
R/W Ñ Read only Ñ
Addr 0xE4E
Figure 6-10. IVEC Register
Table 6-11. IVEC Field Descriptions
Bits Name Description
0Ð2 ILEVEL Interrupt level. The ILEVEL is used to deÞne the interrupt level (0Ð7) associated with the FEC
interrupt (one of the SIU internal interrupt sources).
3 Ñ Reserved. Should be written to zero by the host processor.
4Ð5 Ñ Reserved. Should be written to zero by the host processor.This Þeld may return unpredictable
values and should be masked on a read
6Ð27 Ñ Reserved. Should be written to zero by the host processor.
28Ð29 IVEC Interrupt vector, read only. IVEC gives the highest outstanding priority Fast Ethernet interrupt. The
bit Þeld meanings (from low priority to high priority) are as follows:
00 No pending FEC interrupt
01 Non-time-critical interrupt
10 Transmit interrupt
11 Receive interrupt
30Ð31 Ñ Reserved. Should be written to zero by the host processor.
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