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6-22 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE
6.3 Initialization Sequence
This section describes which registers and RAM locations are reset due to hardware reset,
which are reset due to the microcontroller, and what locations the user must initialize before
enabling the FEC.
6.3.1 Hardware Initialization
In the FEC, only registers that generate interrupts to the PowerPC processor or cause
conßict on bidirectional buses are reset by hardware. The registers shown in Table 6-25 are
reset due to a hardware reset.
Other registers are reset whenever ECNTRL[ETHER_EN] is cleared. Clearing
ETHER_EN immediately stops all DMA accesses and stops transmit activity after a bad
CRC is sent; refer to Table 6-26.
6.3.2 User Initialization (before Setting ECNTRL[ETHER_EN])
The user must initialize portions of the FEC before setting ECNTRL[ETHER_EN]. The
31 GTS Graceful transmit stop. When GTS is set, the MAC stops transmission after any frame being
transmitted is complete and INTR_EVENT[GRA] is set. If frame transmission is not underway, the
GRA interrupt is asserted immediately. When transmission completes, clearing GTS causes the
next frame in the transmit FIFO to be sent. If an early collision occurs during transmission when
GTS = 1, transmission stops after the collision. The frame is sent again once GTS is cleared. Note
that there may be old frames in the transmit FIFO that are sent when GTS is reasserted. To avoid
this, clear ECNTRL[ETHER_EN] after the GRA interrupt.
Table 6-25. Hardware Initialization
User/System Register/Machine Reset Value
User ECNTRL Cleared
User IEVENT Cleared
User IMASK Cleared
User MII.SPEED Cleared
User PORT DPAR Cleared
User PORT DIR Cleared
Table 6-26. ECNTRL[ETHER_EN] Deassertion Initialization
User/System Register/Machine Reset Value
User R_DES_ACTIVE Cleared
User X_DES_ACTIVE Cleared
Table 6-24. X_CNTRL Field Descriptions
Bits Name Description
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Freescale Semiconductor, Inc.
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Go to: www.freescale.com
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