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6-18 MPC860T (Rev. D) Fast Ethernet Controller Supplement MOTOROLA
PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE
Table 6-20 describes X_FSTART Þelds.
6.2.19 DMA Function Code Register (FUN_CODE)
The FUN_CODE register, shown in Figure 6-19, contains the function code and byte order
Þelds to be used during each transfer between the DMA and the SDMA interface. These
bits can be written/read by the user.
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ
Reset 0000_0000_0000_0000
R/W Read/write
Addr 0xEEC
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field Ñ 1 X_FSTART Ñ
Reset 0000_0 1 Microcode dependent 00
R/W Read/write
Addr 0xEEE
Figure 6-18. X_FSTART Register
Table 6-20. X_FSTART Field Descriptions
Bits Name Description
0Ð21 Ñ Reserved. Note that all bits read back as 0 except for 21 which returns a 1.
22Ð29 X_FSTART Address of Þrst transmit FIFO location.
30Ð31 Ñ Reserved. Should be written to zero by the host processor.
Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field Ñ DATA_BO0 DATA_BO1 DESC_BO0 DESC_BO1 FC1 FC2 FC3 Ñ
Reset UndeÞned
R/W Read/write
Addr 0xF34
Bits 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field Ñ
Reset UndeÞned
R/W Read/write
Addr 0xF36
Figure 6-19. FUN_CODE Register
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Freescale Semiconductor, Inc.
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